參數(shù)資料
型號(hào)： LTC3860IUH#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, 1250 kHz SWITCHING FREQ-MAX, PQCC32
封裝： 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32
文件頁數(shù)： 5/36頁
文件大?。?/td> 436K
代理商： LTC3860IUH#PBF
LTC3860
13
3860fc
relationship between channel 1 and CLKOUT, as sum-
marized in Table 2. The phases are calculated relative to
zero degrees, dened as the rising edge of PWM1. Refer
to Applications Information for more details on how to
create multiphase applications.
Table 2. Phase Selection
PHSMD PIN
CH-1 to CH-2 PHASE
CH-1 to CLKOUT PHASE
Float
180°
90°
Low
180°
60°
High
120°
240°
Using the LTC3860 Error Ampliers in
Multiphase Applications
Due to the low output impedance of the error ampliers,
multiphase applications using the LTC3860 use one
error amplier as the master with all of the slaves’
error ampliers disabled. The channel 1 error amplier
(phase = 0°) may be used as the master with phases 2
through n (up to 12) serving as slaves. To disable the
slave error ampliers connect the FB pins of the slaves
to VCC. This three-states the output stages of the ampli-
ers. All COMP pins should then be connected together
to create PWM outputs for all phases. As noted in the
section on soft-start, all TRACK/SS pins should also be
shorted together. Refer to the Multiphase Operation sec-
tion in Applications Information for schematics of various
multiphase congurations.
Theory and Benets of Multiphase Operation
Multiphase operation provides several benets over tra-
ditional single phase power supplies:
n Greater output current capability
n Improved transient response
n Reduction in component size
n Increased real world operating efciency
Because multiphase operation parallels power stages,
the amount of output current available is n times what it
would be with a single comparable output stage, where n
is equal to the number of phases.
The main advantages of PolyPhase operation are ripple
current cancellation in the input and output capacitors, a
faster load step response due to a smaller clock delay and
reduced thermal stress on the inductors and MOSFETs
due to current sharing between phases. These advantages
allow for the use of a smaller size or a smaller number
of components.
Power Good Indicator Pins (PGOOD1, PGOOD2)
Each PGOOD pin is connected to the open drain of an
internal pull-down device which pulls the PGOOD pin
low when the corresponding FB pin voltage is outside
the PGOOD regulation window (±7.5% entering regula-
tion, ±10% leaving regulation). The PGOOD pins are also
pulled low when the corresponding RUN pin is low, or
during UVLO.
In multiphase applications, one FB pin and error amplier
are used to control all of the phases. PGOOD outputs for
the slave phases may be left unconnected as they will not
report fault conditions.
PWM and PWMEN Pins
The PWM pins are three-state compatible outputs, de-
signed to drive MOSFET drivers, DRMOSs, etc which do
not represent a heavy capacitive load. An external resistor
divider may be used to set the voltage to mid-rail while in
the high impedance state.
The PWMEN outputs have an open-drain pull-up to VCC and
require an appropriate external pull-down resistor. This pin
is intended to drive the enable pins of the MOSFET driv-
ers that do not have three-state compatible PWM inputs.
PWMEN is low only when PWM is high impedance, and
high at any other PWM state.
OPERATION (Refer to Functional Diagram)
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