參數(shù)資料
型號(hào)： LTC3860IUH#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, 1250 kHz SWITCHING FREQ-MAX, PQCC32
封裝： 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32
文件頁(yè)數(shù)： 2/36頁(yè)
文件大?。?/td> 436K
代理商： LTC3860IUH#PBF
LTC3860
10
3860fc
OPERATION (Refer to Functional Diagram)
Main Control Architecture
The LTC3860 is a dual-channel/dual-phase, constant
frequency, voltage mode controller for DC/DC step-down
applications. It is designed to be used in a synchronous
switching architecture with external integrated-driver
MOSFETs or external drivers and N-channel MOSFETs
using single wire three-state PWM interfaces. The
controller allows the use of sense resistors or lossless
inductor DCR current sensing to maintain current balance
between phases and to provide overcurrent protection.
The operating frequency is selectable from 250kHz to
1.25MHz. To multiply the effective switching frequency,
multiphase operation can be extended to 3, 4, 6, or 12
phases by paralleling up to 6 controllers. In single or 3-
phase operation, the 2nd or 4th channel can be used as
an independent output.
The output of the differential amplier is connected to
the error amplier inverting input (FB) through a resistor
divider. The remote sense differential amplier output
(VSNSOUT)providesasignalequaltothedifferentialvoltage
(VSNSP – VSNSN) sensed across the output capacitor, but
re-referenced to the local ground (SGND). This permits
accurate voltage sensing at the load, without regard to
the potential difference between its ground and local
ground.
In the main voltage mode control loop, the error ampli-
er output (COMP) directly controls the converter duty
cycle in order to drive the FB pin to 0.6V in steady state.
Dynamic changes in output load current can perturb the
output voltage. When the output is below regulation,
COMP rises, increasing the duty cycle. If the output rises
above regulation, COMP will decrease, decreasing the
duty cycle. As the output approaches regulation, COMP
will settle to the steady-state value representing the step-
down conversion ratio.
In normal operation, the PWM latch is set high at the begin-
ning of the clock cycle (assuming COMP > 0.5V). When
the (line feedforward compensated) PWM ramp exceeds
the COMP voltage, the comparator trips and resets the
PWM latch. If COMP is less than 0.5V at the beginning
of the clock cycle, as in the case of an overvoltage at the
outputs, the PWM pin remains low throughout the entire
cycle. When the PWM pin goes high it has a minimum
on-time of approximately 20ns and a minimum off-time
of approximately 1/12th the switching period.
Current Sharing
In multiphase operation, the LTC3860 also incorporates an
auxiliary current sharing loop. Inductor current is sampled
each cycle. The master’s current sense amplier output
is averaged at the IAVG pin. A small capacitor connected
from IAVG to GND (typically 100pF) stores a voltage cor-
responding to the instantaneous average current of the
master. Each phase integrates the difference between its
current and the master’s. Within each phase the integrator
output is proportionally summed with the system error
amplier voltage (COMP), adjusting that phase’s duty
cycle to equalize the currents. When multiple ICs are
daisychained the IAVG pins must be connected together.
When the phases are operated independently, the IAVG
pin should be tied to ground. Figure 1 shows a transient
load step with 50% inductor mismatch in a 2-phase system.
Figure 1
VOUT(AC)
100mV/DIV
50μs/DIV
3860 F01
VIN = 12V
VOUT = 1.2V
ILOAD = 0A TO 25A
IL1 = 320nH
10A/DIV
ILOAD
20A/DIV
IL2 = 220nH
10A/DIV
Overcurrent Protection
The current sense amplier outputs also connect to
overcurrent (OC) comparators that provide fault protec-
tion in the case of an output short. When an OC fault is
detected, the controller three-states the PWM output,
resets the soft-start capacitor, and waits for 32768 clock
cycles before attempting to start up again. The LTC3860
also provides negative OC (NOC) protection by preventing
turn-on of the bottom MOSFET during a negative OC fault
condition. The negative OC threshold is equal to –3/4 the
positive OC threshold. See Applications Information for
guidelines on setting these thresholds.
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