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參數(shù)資料
| 型號： | LTC3858EUH-2#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, 900 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 432K |
| 代理商： | LTC3858EUH-2#PBF |
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LTC3858-2
14
38582f
OPERATION (Refer to the Functional Diagram)
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3858-2 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with the
LTC3858-2 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 2. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the top
gate driver output of controller 1 (TG1). The CLKOUT pin
swings from ground to INTVCCwithapull-downimpedance
of 120Ω and a pull-up impedance of 150Ω.
Table 2
VPHASMD
CONTROLLER 2-PHASE
CLKOUT PHASE
GND
180°
60°
Floating
180°
90°
INTVCC
240°
120°
Output Overvoltage Protection
An overvoltage (OV) comparator guards against transient
overshoots as well as other more serious conditions that
may overvoltage the output. When the VFB pin rises by
more than 10% above its regulation point of 0.800V, the
top MOSFET is turned off until the overvoltage condition
is cleared.
The state of the bottom MOSFET during the overvoltage
condition depends on the light load mode of operation,
as selected by the PLLIN/MODE pin. In forced continu-
ous mode, the bottom gate driver BG naturally turns on
whenever the top gate driver TG is off, resulting in nega-
tive inductor current which discharges the output to (try
to) bring it back into regulation. In pulse-skipping mode,
BG is held off most of the time but is turned on for a brief
pulse every ten clock cycles (for an effective BG-on duty
cycle of ~1%) to refresh the BOOST-SW capacitor. This
causes a slightly negative average inductor current which,
in addition to whatever load current is present, may slowly
discharge the output. In Burst Mode operation, BG is held
off continuously, leaving only the load current to discharge
the output to bring it back into regulation.
Power Good (PGOOD1 and PGOOD2) Pins
Each PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the corresponding VFB pin
voltage is not within ±10% of the 0.8V reference voltage.
The PGOOD pin is also pulled low when the corresponding
RUN pin is low (shut down). When the VFB pin voltage
is within the ±10% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source no greater than 6V.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
TRACK/SS voltage).
Theory and Benefits of 2-Phase Operation
Why the need for 2-phase operation? Up until the 2-phase
family, constant frequency dual switching regulators
operated both channels in phase (i.e., single phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dual
switching regulator are operated 180 degrees out of phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
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