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參數資料
| 型號： | LTC3833IFE#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | 4.40 MM, LEAD FREE, PLASTIC, TSSOP-20 |
| 文件頁數： | 21/36頁 |
| 文件大?。?/td> | 513K |
| 代理商： | LTC3833IFE#PBF |
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LTC3833
28
3833f
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3833.
Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking
purposes. Use wide rails and/or entire planes for VIN,
VOUT and PGND nodes for good filtering and minimal
copper loss. If a ground layer is used, then it should
be immediately below (and/or above) the routing layer
for the power train components which consist of CIN,
power MOSFETs, inductor, sense resistor (if used) and
COUT. Flood unused areas of all layers with copper for
better heat sinking.
Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a nar-
row PCB trace (or single via in a multilayer board). All
power train components should be referenced to power
ground and all small-signal components (e.g., CITH1,
RT, CSS etc.) should be referenced to signal ground.
Place CIN, power MOSFETs, inductor, sense resistor (if
used), and primary COUT capacitors close together in
one compact area. The SW node should be compact
but be large enough to handle the inductor currents
without large copper losses. Connect the drain of the
topside MOSFET as close as possible to the (+) plate of
CIN capacitor(s) that provides the bulk of the AC current
(these are normally the ceramic capacitors), and con-
nect the source of the bottom side MOSFET as close as
possibletothe(–)terminalofthesameCINcapacitor(s).
The high dI/dt loop formed by CIN, the top MOSFET,
and the bottom MOSFET should have short leads and
PCB trace lengths to minimize high frequency EMI and
voltage stress from inductive ringing. The (–) terminal
of the primary COUT capacitor(s) which filter the bulk
of the inductor ripple current (these are normally the
ceramic capacitors) should also be connected close to
the (–) terminal of CIN.
Place BOOST, TG, SW, BG and PGND pins facing the
power train components. Keep high dV/dt signals on
BOOST,TG,SWandBGawayfromsensitivesmall-signal
traces and components.
For RSENSE current sensing, place the sense resistor
close to the inductor on the output side. Use a Kelvin
(4-wire) connection across the sense resistor and
route the traces together as a differential pair. RC filter
the differential sense signal close to SENSE+/SENSE–
pins, placing the filter capacitor as close as possible
to the pins. For DCR sensing, Kelvin connect across
the inductor and place the DCR sensing resistor closer
to the SW node and further away from the SENSE+/
SENSE– pins. Place the DCR capacitor close to the
SENSE+/SENSE– pins.
Place the resistive feedback divider RFB1/2 as close as
possible to VOSNS+/VOSNS– pins and route the remote
output and ground traces together as a differential
pair and terminate as close to the regulation point as
possible(preferablyKelvinconnectacrossthecapacitor
at the remote output point).
Place the ceramic CVCC capacitor as close as possible
to INTVCC and PGND pins. Likewise, the CB capacitor
should be as close as possible to BOOST and SW pins.
These capacitors provide the gate charging currents for
the power MOSFETs.
Placesmall-signalcomponentsasclosetotheirrespec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
VOSNS+/VOSNS–, SENSE+/SENSE–, ITH, RT and VRNG
pins.Usesufficientisolationwhenroutingaclocksignal
into MODE/PLLIN pin so that the clock does not couple
into sensitive small-signal pins.
Filter the VIN input to the LTC3833 with a simple RC
filter close to the pin. The RC filter should be referenced
to signal ground.
APPLICATIONS INFORMATION
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