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參數(shù)資料
| 型號： | LTC3833IFE#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | 4.40 MM, LEAD FREE, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 513K |
| 代理商： | LTC3833IFE#PBF |
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LTC3833
24
3833f
APPLICATIONS INFORMATION
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3833, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current mode
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
ILIMIT =
VSENSE(MAX)
RSENSE
+
1
2
IL
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest VIN
and highest ambient temperature. It is important to check
for consistency between the assumed MOSFET junction
temperatures and the resulting value of ILIMIT which heats
the MOSFET switches.
To further limit current in the event of a short circuit to
ground, the LTC3833 includes foldback current limiting.
If the output fails by more than 50%, then the maximum
sensevoltageisprogressivelyloweredtoaboutone-fourth
of its full value.
If the output exceeds 7.5% of the programmed value,
then it is considered as an overvoltage (OV) condition.
In such a case, the top MOSFET is immediately turned
off and the bottom MOSFET is turned on indefinitely until
the OV condition is removed. Current limiting is not active
during an OV. If the output returns to a nominal level, then
normal operation resumes. If the OV persists a long time,
the current through the bottom MOSFET and inductor
could exceed their maximum ratings.
OPTI-LOOP Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
but also provides a test point for the step-down regulator’s
DC-coupled and AC-filtered closed-loop response. The DC
step,risetimeandsettlingatthistestpointtrulyreflectsthe
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
TheITHseriesRITH-CITH1filtersetsthedominantpole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to SGND, CITH2, may be required to at-
tenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT im-
mediatelyshiftsbyanamountequalto
ILOADESR,where
ESR is the effective series resistance of COUT. ILOAD also
begins to charge or discharge COUT,generatingafeedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
anddrivingthegatewithanappropriatesignalgeneratoris
a practical way to produce a realistic load-step condition.
Theinitialoutputvoltagestepresultingfromthestepchange
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated feedback loop response.
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