參數(shù)資料
型號： LTC2442IG
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述： 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36
封裝： 5.30 MM, PLASTIC, SSOP-36
文件頁數(shù)： 5/32頁
文件大?。?/td> 392K
代理商： LTC2442IG
LTC2442
5
2442f
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
V
CC
= 4.5V to 5.5V unless otherwise specified.
V
REF
= REF
+
– REF
–
, V
REFCM
= (REF
+
+ REF
–
)/2;
V
IN
= SEL
+
– SEL
–
, V
INCM
= (SEL
+
+ SEL
–
)/2.
Note 4:
F
O
pin tied to GND or to external conversion clock source with
f
EOSC
= 10MHz unless otherwise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
The converter uses the internal oscillator.
Note 8:
The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
ESCK
and is expressed in Hz.
Note 9:
The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of C
LOAD
= 20pF.
Note 10:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in Hz.
Note 11:
The converter uses the internal oscillator. F
O
= 0V.
Note 12:
Guaranteed by design and test correlation.
Note 13:
There is an internal reset that adds an additional 1μs (typ) to the
conversion time.
Note 14:
In order to achieve optimum linearity, the amplifier power
positive supply input (V
+
) must exceed the maximum input voltage level by
2V or greater. The negative amplifier power supply input (V
–
) must be at
least 200mV below the minimum input voltage level.
Note 15:
Amplifiers are externally compensated with 0.1μF.
TIW
U
range, otherwise specifications are at T
A
= 25°C. (Note 3)
SYMBOL
PARAMETER
f
EOSC
External Oscillator Frequency Range
t
HEO
External Oscillator High Period
t
LEO
External Oscillator Low Period
t
CONV
Conversion Time
The
●
denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
0.1
25
25
0.99
126
TYP
MAX
20
10000
10000
1.33
170
UNITS
MHz
●
●
ns
ns
ms
ms
●
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
External Oscillator (Notes 10, 13)
●
●
●
1.13
145
40 OSR + 170
f
EOSC
(KHz)
0.9
f
EOSC
/10
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
(Note 9)
(Note 8)
(Note 8)
(Note 8)
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
(Note 8)
(Note 12)
(Note 12)
(Note 9)
(Note 8, 12)
●
0.8
1
MHz
Hz
D
ISCK
f
ESCK
fLESCK
t
HESCK
t
DOUT_ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 32-Bit Data Output Time
●
45
55
20
%
●
MHz
ns
ns
μs
●
25
25
30.9
●
●
●
35.3
320/f
EOSC
32/f
ESCK
41.6
s
s
t
DOUT_ESCK
t
1
t
2
t
3
t
4
t
KQMAX
t
KQMIN
t
5
t
6
t
7
t
8
External SCK 32-Bit Data Output Time
CS
↓
to SDO Low Z
CS
↑
to SDO High Z
CS
↓
to SCK
↓
CS
↓
to SCK
↑
SCK
↓
to SDO Valid
SDO Hold After SCK
↓
SCK Setup Before CS
↓
SCK Hold After CS
↓
SDI Setup Before SCK
↑
SDI Hold After SCK
↑
●
●
0
0
25
25
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
●
5
●
25
●
25
(Note 5)
●
15
50
●
●
50
(Note 5)
(Note 5)
●
10
10
●
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