參數(shù)資料
型號(hào): LTC2442IG
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述: 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36
封裝: 5.30 MM, PLASTIC, SSOP-36
文件頁數(shù): 24/32頁
文件大?。?/td> 392K
代理商: LTC2442IG
LTC2442
24
2442f
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC
4
digital filter and
the digital and analog autocalibration circuits determines
the LTC2442 input bandwidth and rejection characteristics.
The digital filter’s response can be adjusted by setting the
oversample ratio (OSR) through the SPI interface or by
supplying an external conversion clock to the f
O
pin.
Table 7 lists the properties of the LTC2442 with various
combinations of oversample ratio and clock frequency.
Understanding these properties is the key to fine tuning
the characteristics of the LTC2442 to the application.
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
First Notch Frequency
This is the first notch in the SINC
4
portion of the digital filter
and depends on the fo clock frequency and the oversample
ratio. Rejection at this frequency and its multiples (up to
the modulator sample rate of 1.8MHz) exceeds 120dB.
This is 8 times the maximum conversion rate.
Effective Noise Bandwidth
The LTC2442 has extremely good input noise rejection from
the first notch frequency all the way out to the modulator
sample rate (typically 1.8MHz). Effective noise bandwidth
is a measure of how the ADC will reject wideband input
noise up to the modulator sample rate
Table 7
Over-
sample
Ratio
(OSR)
*RMS
Noise
ENOB
(V
REF
= 5V)
Maximum
Conversion Rate
Internal
9MHz clock
3515.6
1757.8
878.9
439.5
219.7
109.9
54.9
27.5
13.7
6.9
First Notch
Frequency
Internal
9MHz clock
28125
14062.5
7031.3
3515.6
1757.8
878.9
439.5
219.7
109.9
54.9
Effective
Noise BW
–3dB
point (Hz)
External
f
0
f
0
/2560
f
0
/5120
f
0
/10240
f
0
/20480
f
0
/40960
f
0
/81920
f
0
/163840
f
0
/327680
f
0
/655360
f
0
/1310720
External
f
0
f
0
/320
f
0
/640
f
0
/1280
f
0
/2560
f
0
/5120
f
0
/1020
f
0
/2050
f
0
/4100
f
0
/8190
f
0
/16380
Internal
9MHz clock
3148
1574
787
394
197
98.4
49.2
24.6
12.4
6.2
External
f
0
f
0
/5710
f
0
/2860
f
0
/1140
f
0
/2280
f
0
/4570
f
0
/9140
f
0
/18300
f
0
/36600
f
0
/73100
f
0
/146300
Internal
9MHz clock
1696
848
424
212
106
53
26.5
13.2
6.6
3.3
External
f
0
f
0
/5310
f
0
/10600
f
0
/21200
f
0
/42500
f
0
/84900
f
0
/170000
f
0
/340000
f
0
/679000
f
0
/1358000
f
0
/2717000
64
128
256
512
1024
2048
4096
8192
16384
32768
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 64 include effects
from internal modulator quantization noise.
23μV
3.6μV
2.1μV
1.5μV
1.2μV
840nV
630nV
430nV
305nV
220nV
17.7
20.4
21.2
21.6
22
22.5
22.4
23.5
24
24.4
APPLICATIU
W
U
U
29
2
30
1
36
6
7
35
3
2442 F14
34
4,5,32
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT
–0.5V
TO
0.5V
REF
3-WIRE
SPI INTERFACE
4.5V TO 5.5V
31
V
CC
BUSY
F
O
REF
+
SCK
CH0
CH1
SDO
GND
CS
EXT
LTC2442
REF
1
μ
F
0.1
μ
F
LTC1799
OUT
DIV
SET
GND
V
+
R
SET
NC
Figure 14. Simple External Clock Source
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