參數(shù)資料
型號: LTC2442IG
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述: 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO36
封裝: 5.30 MM, PLASTIC, SSOP-36
文件頁數(shù): 29/32頁
文件大?。?/td> 392K
代理商: LTC2442IG
LTC2442
29
2442f
APPLICATIU
Details of the Conversion and Autozero Process
The LTC2442 performs automatic offset cancellation for
each conversion. This is accomplished by taking the aver-
age of two “half-conversions” with the inputs applied in
opposite polarity. Figure 21 shows a conversion on CH0 to
CH1 differential at OSR of 32768, in 1x mode. This chan-
nel is selected by sending the appropriate configuration
word to the LTC2442 through the SPI interface. On the
13
th
falling clock edge, the CH0 input is applied to +INA
through the multiplexer and CH1 is connected to +INB.
The outputs of the amplifiers slew during the remainder
of the data I/O state and the conversion begins on the
W
U
U
32
nd
falling clock edge. Halfway through the conversion
(approximately 73ms later) the multiplexer switches the
CH0 input to +INB and the CH1 input to +INA. The digital
filter subtracts the two half-conversions, which removes
the offset of the amplifiers and converter.
At the end of a conversion, the multiplexer assumes that
the next conversion will be on the same channel and
switches back to the opposite polarity on the channel just
converted. This gives extra settling time when convert-
ing on one channel continuously. If a different channel is
programmed, the multiplexer will switch again on the 13
th
falling clock edge.
OUTB
OUTA
BUSY
SCK
CS
Figure 21. Amplifier Outputs and CS, SCK, BUSY During a Conversion
on CH0-1, OSR32768. V
INDIFF
= 2.5V, V
CM
= 2.5V
20ms/DIV
2V/DIV
5V/DIV
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