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參數(shù)資料
| 型號： | LTC1759 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Octal D-Type Edge-Triggered Read-Back Latches 24-SOIC 0 to 70 |
| 中文描述： | 智能電池充電器 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | LTC1759 |
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26
LTC1759
APPLICATIO
S I
FOR
ATIO
U
below ground with the full battery potential, causing a
potential for latch-up in any of the devices connected to the
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 13.
W
U
U
M3
1759 F11
M4
TPO610
R
S4
INFET
LTC1759
V
CC
V
IN
Figure 12. V
BAT
Crowbar Protection
Figure 11. V
IN
Crowbar Protection
1759 F12
SDB
LTC1759
D5
1N4148
100k
V
BAT
CHGEN
CONNECTOR
TO BATTERY
TO SYSTEM
1759 F13
FOR ESD PROTECTION
FOR ESD AND LATCH-UP
PROTECTION
V
DD
Figure 13
PCB Layout Considerations
The LTC1759 has two layout critical areas. The first is the
I
SET
pin and the second is the DC/DC converter switching
circuity.
I
SET
Pin Layout:
The LTC1759 I
SET
pin lead length is
critical and should be kept to a minimum to reduce
parasitic capacitance. Any parasitic capacitance on this
node will cause errors in the programmed current values.
Place R
SET
resistor directly next to the I
SET
pad. The trace
from R
SET
to the LTC1759 PROG pin pad is not critical.
DC/DC PCB Layout Hints:
For maximum efficiency, the
switch node rise and fall time is kept as short as possible.
To prevent magnetic and electrical field radiation and high
frequency resonant problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary and secondary).
1. Keep the highest frequency loop path as small and tight
as possible. This includes the bypass capacitors, with
the higher frequency capacitors being closer to the
noise source than the lower frequency capacitors. The
highest frequency power path loop has the highest
layout priority. For best results, avoid using vias in this
loop and keep the entire high frequency loop on a single
external PCB layer. If you must, use multiple vias to
keep the impedance down (see Figure 15).
2. Run long power traces in parallel. Best results are
achieved if you run each trace on separate PCB layer
one on top of the other for maximum capacitance
coupling and common mode noise rejection.
3. If possible, use a ground plane under the switcher
circuitry to minimize capacitive interplane noise cou-
pling.
4. Keep signal or analog ground separate. Tie this analog
ground back to the power supply at the output ground
using a single point connection.
5. For best current programming accuracy provide a Kelvin
connection from R
SENSE
to R
S1
and R
S2
. See Figure 14
as an example.
Interfacing with a Selector
The LTC1759 is designed to be used with a true analog
multiplexer for the thermistor sensing path. Some selec-
tor ICs from various manufacturers may not implement
this. Consult LTC applications department for more infor-
mation.
Electronic Loads
The LTC1759 is designed to work with a real battery.
Electronic loads will create instability within the LTC1759
preventing accurate programming currents and voltages.
Consult LTC applications department for more informa-
tion.
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