參數(shù)資料
型號: LTC1406
廠商: Linear Technology Corporation
英文描述: Low Power, 8-Bit, 20Msps, Sampling A/D Converter(低功耗,12位, 20Msps,采樣模數(shù)轉(zhuǎn)換器)
中文描述: 低功耗,8位,20Msps,采樣A / D轉(zhuǎn)換器(低功耗,12位,20Msps,采樣模數(shù)轉(zhuǎn)換器)
文件頁數(shù): 6/16頁
文件大小: 367K
代理商: LTC1406
6
LTC1406
PI
FU
CTIO
N
S
U
U
AV
DD
(Pin 9):
Analog 5V Positive Supply.
Bypass to ana-
log ground plane with 10
μ
F tantalum in parallel with 0.1
μ
F
or 10
μ
F ceramic.
AGND (Pin 10):
Analog Ground. Tie to analog ground plane.
DGND (Pin 11):
Digital Ground for Internal Logic. Tie to
analog ground plane.
DV
DD
(Pin 12):
Digital 5V Positive Supply.
Bypass to DGND
with 10
μ
F tantalum in parallel with 0.1
μ
F or 10
μ
F ceramic.
NC (Pins 13, 14):
No Internal Connection.
D7 to D0 (Pins 15 to 22):
Digital Data Outputs. The out-
puts swing between OV
DD
and OGND.
OF/UF (Pin 23):
Overflow/Underflow Bit. OF/UF high with
D7 to D0 all high indicates an overrange, OF/UF high with
D7 to D0 all low indicates an underrange condition. OF/UF
low indicates a conversion within the normal input range.
The outputs swing between OV
DD
and OGND.
CLK (Pin 24):
Clock Input. Internal sample-and-hold tracks
the input signal when CLK is high and samples the input
signal on the falling edge.
AV
DD
= DV
DD
= V
DD
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13 to 14
15 to 22
23
24
NOMINAL (V)
TYP
0
3 or 5
ABSOLUTE MAXIMUM (V)
MAX
MIN
–0.3
5.25
–0.3
V
DD
–0.3
2.5
–0.3
3
–0.3
–0.3
V
DD
–0.3
V
DD
–0.3
5.25
–0.3
–0.3
–0.3
5.25
–0.3
NAME
OGND
OV
DD
SHDN
V
BIAS
V
REF
AGND
A
IN+
A
IN–
AV
DD
AGND
DGND
DV
DD
NC
D7 to D0
OF/UF
CLK
DESCRIPTION
Ground for Output Drivers
Supply for Output Drivers
Shutdown Input, Active Low
Internal Bias Voltage
External Reference Input
Analog Ground, Clean Ground
Positive Analog Input,
±
1V Span
Negative Analog Input
Analog Supply
Analog Ground, Substrate Ground
Digital Ground
Digital Supply
No Connect, No Internal Connection
Data Outputs
Overflow/Underflow Output
Clock Input
MIN
MAX
V
DD
+ 0.3
6
10
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
6
V
DD
+ 0.3
V
DD
+ 0.3
6
2.7
0
1.9
2
2.2
2.5
0
0
0
4.75
5
0
0
5
4.75
OGND
OGND
0
OV
DD
OV
DD
V
DD
–0.3
–0.3
–0.3
V
DD
+ 0.3
V
DD
+ 0.3
10
TIW
W
ANALOG
SIGNAL
CLOCK
N – 1
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
1406 TD
N
t
6
N + 1
DATA OUT
t
3
t
1
t
2
N + 2
N + 3
N + 4
N + 6
N + 5
t
4
t
5
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