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參數(shù)資料
| 型號： | LTC1406 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Low Power, 8-Bit, 20Msps, Sampling A/D Converter(低功耗,12位, 20Msps,采樣模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 低功耗，8位，20Msps，采樣A / D轉(zhuǎn)換器（低功耗，12位，20Msps，采樣模數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 367K |
| 代理商： | LTC1406 |
12
LTC1406
APPLICATIO
S I
FOR
ATIO
U
common mode voltage minus 3.90625mV (i.e., –0.5LSB)
and adjust the offset at the A
IN–
input until the output code
flickers between 0111 1111 and 1000 0000. For full-scale
adjustment, an input voltage equal to the input common
mode voltage plus 988.28125mV (i.e., FS – 1.5LSBs) is
applied to A
IN+
and the V
REF
input is adjusted until the
output code flickers between 1111 1110 and 1111 1111.
W
U
U
While the falling edge starts the conversion, both rising
and falling edges are used internally during the conver-
sion. It is therefore important to provide a clock signal that
has low jitter and fast rise and fall times (<2ns). Much of
the internal circuitry operates dynamically limiting the mini-
mum conversion rate to 10kHz. To ensure proper opera-
tion after power is first applied, or the clock stops for more
than 100
μ
s, typically 20 clock cycles must be performed
at a sample rate above 10kHz before the output data will
be valid.
Digital Inputs and Outputs
The LTC1406 is designed to easily interface with either 3V
or 5V logic. The digital input pins, SHDN and CLK, have
thresholds of nominally 1.9V and will accept a 3V or 5V
logic input. The data output pins, including OF/UF, are
connected to a separate supply and ground (OV
DD
and
OGND respectively). OV
DD
is normally connected to DV
DD
but can be connected to an external supply as low as 2.7V.
OGND is normally connected to DGND but can be con-
nected to an external ground or an external voltage source
as high as 2V.
Clock
The LTC1406 requires a 50% duty cycle clock. The duty
cycle should be timed from the nominal threshold of the
CLK input which is 1.9V. At conversion speeds below the
maximum conversion rate of 20MHz, the duty cycle can
deviate from 50% with no degradation in performance as
long as each clock phase is at least 25ns long. At the
maximum conversion rate, deviation from a 50% duty cycle
clock results in interstage settling times of <25ns and
performance may be affected.
With the CLK pin high, the ADC will track the difference of
the two analog inputs. On the falling edge of CLK the input
is sampled and the conversion begins. At the end of five
clock cycles (on the fifth falling CLK edge following the
start of conversion) the data from the conversion will be
available at the digital outputs until the next falling CLK
edge. Each falling edge of CLK starts a new conversion so
successive conversion results are available on successive
falling CLK edges.
Figure 11. Typical DNL vs Duty Cycle
DUTY CYCLE (%)
28
D
10
9
8
7
6
5
4
3
2
1
0
64 68
1406 F11
36 40
32
44 48 52 56 60
72
f
SAMPLE
= 20MHz
Power Shutdown
The quiescent power of the LTC1406 can be further
reduced between conversions by taking the SHDN pin low.
This powers down all of the internal amplifiers and bias
circuitry and the part draws only a small quiescent current
of 1
μ
A from the 5V supply. There is a nominally 4k internal
resistor between V
REF
and AGND that will continue to draw
current during shutdown as long as V
REF
is driven. It should
also be noted that the data output drivers are not three-
state devices and do not go into a high impedance state
during shutdown. If the data output pins will remain con-
nected to a load during shutdown, current may be drawn
through the OV
DD
supply pin. This can be prevented by
including a FET switch in series with OV
DD
or OGND con-
trolled by SHDN. If the data bus will remain active during
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