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參數(shù)資料
| 型號： | LTC1404 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Complete SO-8, 12-Bit, 600ksps ADC with Shutdown(SO-8封裝，12位,600ksps，模數(shù)轉(zhuǎn)換器（帶關(guān)斷）) |
| 中文描述： | 完整的SO - 8，12位，600ksps ADC的與關(guān)斷（以SO - 8封裝，12位，600ksps，模數(shù)轉(zhuǎn)換器（帶關(guān)斷）） |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 392K |
| 代理商： | LTC1404 |
4
LTC1404
(Note 5)
DIGITAL U
D OUTPUTS
U
SYMBOL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Source Current
Output Sink Current
CONDITIONS
V
OUT
= 0V to V
CC
MIN
TYP
MAX
±
10
UNITS
G
μ
A
pF
mA
mA
15
–10
10
V
OUT
= 0V
V
OUT
= V
CC
TW U
(Note 5, see Figures 12, 13, 14)
The
G
denotes specifications which apply over the full operating
temperature range; all other limits and typicals apply to T
A
= 25
°
C.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
When these pin voltages are taken below V
SS
(ground for unipolar
mode) or above V
CC
, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA without latch-up if the pin is
driven below V
SS
(ground for unipolar mode) or above V
CC
.
Note 4:
When these pin voltages are taken below V
SS
(ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA without latch-up if the pin is driven
below V
SS
(ground for unipolar mode). These pins are not clamped to V
CC
.
Note 5:
V
CC
= 5V, f
SAMPLE
= 600kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 8:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 9:
Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 10:
The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance, ensure that CONV returns low either within 100ns
after the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time (Unipolar Mode)
CONDITIONS
MIN
600
TYP
MAX
UNITS
kHz
G
f
CLK
= 9.6MHz
1.36
200
160
μ
s
ns
ns
(Bipolar Mode V
SS
= –5V)
f
CLK
t
CLK
t
WK(NAP)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
CLK Frequency
CLK Pulse Width
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV
↑
to CLK
↑
Setup Time
CONV
↑
After Leading CLK
↑
CONV Pulse Width
Time from CLK
↑
to Sample Mode
Aperture Delay of Sample-and-Hold
Minimum Delay Between Conversion (Unipolar Mode)
G
0.1
40
9.6
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 6)
G
350
G
40
70
0
40
G
G
(Note 10)
G
60
40
220
180
40
40
30
Jitter < 50ps
(Note 6)
G
G
310
300
70
70
(Bipolar Mode V
SS
= –5V)
t
8
t
9
t
10
Delay Time, CLK
↑
to D
OUT
Valid
Delay Time, CLK
↑
to D
OUT
Hi-Z
Time from Previous Data Remains Valid After CLK
↑
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
G
G
G
10
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