參數(shù)資料
型號(hào): LTC1297
廠商: Linear Technology Corporation
英文描述: Single Chip 12-Bit Data Acquisition Systems(5V,單片,12位數(shù)據(jù)采集系統(tǒng)(內(nèi)置采樣和保持))
中文描述: 單芯片12位數(shù)據(jù)采集系統(tǒng)(5V的,單片,12位數(shù)據(jù)采集系統(tǒng)(內(nèi)置采樣和保持))
文件頁數(shù): 15/24頁
文件大?。?/td> 398K
代理商: LTC1297
15
LTC1292/LTC1297
U
S
A
O
PPLICATI
U
U
Figure 11b. Setup Time (t
suCS
) Is Met for the LTC1292
Figure 11c. Setup Time (t
suCS
) Is Not Met for the LTC1292
t
suCS
. With the minimum possible sample time of 6
μ
s,
R
SOURCE
+ < 5k and C1 < 20pF will provide adequate
settling time
. In general for both the LTC1292 and LTC1297
keep the product of the total resistance and the total
capacitance less than t
SMPL
/9. If this condition can not be
met, then make C1 > 0.47
μ
F (see RC Input Filtering
section).
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 11a,
11b, 11c and 12). During the conversion, the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. It is critical that the
D
OUT
CLK
B11
HI-Z
B9
B10
LTC1292/7 F11b
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
D
OUT
CLK
B11
HI-Z
B10
LTC1292/7 F11c
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
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