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參數(shù)資料
| 型號(hào)： | LTC1297 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Single Chip 12-Bit Data Acquisition Systems(5V，單片，12位數(shù)據(jù)采集系統(tǒng)(內(nèi)置采樣和保持)) |
| 中文描述： | 單芯片12位數(shù)據(jù)采集系統(tǒng)（5V的，單片，12位數(shù)據(jù)采集系統(tǒng)（內(nèi)置采樣和保持）） |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 398K |
| 代理商： | LTC1297 |
11
LTC1292/LTC1297
on two port lines and the D
OUT
signal is read on a third port
line. After a falling CLK edge each data bit is loaded into the
carry bit and then rotated into the accumulator. Once the
first 8 MSBs have been shifted into the accumulator they
are loaded into register R2. The last four bits are shifted in
the same way and loaded into register R3. The output data
is left-justified in registers R2 and R3 (Figure 5).
For the LTC1297 four NOPs need to be inserted in the 8051
code after CS goes low to allow the LTC1297 to wake up
from power shutdown (t
suCS
).
U
S
A
O
PPLICATI
U
U
LABEL MNEMONIC
LDAA
STAA
LDAA
STAA
LDAA
OPERAND
#$50
$1028
#$1B
$1009
#$00
COMMENTS
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DUMMY DIN WORD INTO
ACC A
LOAD DUMMY DIN DATA INTO $0
LOAD INDEX REGISTER X WITH
$1000
LOAD ACC B WITH $00
LOAD DIN INTO ACC FROM $50
D0 GOES LOW (CS GOES LOW)
3 NOP FOR t
suCS
TIMING
STAA
LDX
$50
#$1000
LOOP
LDAB
LDAA
BCLR
NOP
NOP
NOP
STAA
#$00
$50
$08,X,$01
$102A
LOAD DUMMY DIN INTO SPI,
START CLK
LABEL MNEMONIC
LOOP1 LDAA
BPL
LDAA
STAA
STAA
OPERAND
$1029
LOOP1
$102A
$61
$102A
COMMENTS
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1297 MSBs INTO ACC A
STORE MSBs IN $61
LOAD DUMMY DIN INTO SPI,
START SCK
CHECK SPI STATUS RES
CHECK IF TRANSFER IS DONE
D0 GOES HIGH (CS GOES HIGH)
LOAD LTC1297 LSBs INTO ACC A
STORE LSBs IN $62
ROTATE RIGHT WITH CARRY
NEEDED TO RIGHT JUSTIFY
THE DATA IN $61 AND $62
MC68HC11 CODE for LTC1297 Interface
LOOP2 LDAA
$1029
LOOP2
$08X,$01
$102A
$62
$61
$62
$61
$62
LOOP
BPL
BSET
LDAA
STAA
ROR
ROR
ROR
ROR
JMP
START NEXT CONVERSION
BYTE 2
B3
B7
B6
B5
B4
B2
B0
B1
B10
B9
B8
B11
O
O
O
O
BYTE 1
D
OUT
FROM LTC1297 STORED ON MC68HC11 RAM
LOCATION #61
LOCATION #62
MSB
LTC1292/7 F04
CLK
D
OUT
LTC1297
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
Figure 4. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
The data is right- justified in the two memory locations by
rotating right twice (Figure 4). ANDing the first byte with
0F
HEX
clears the four most significant bits. This operation
was not included in the code. It can be inserted in the data
gathering loop or outside the loop when the data is
processed.
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1292/LTC1297 and parallel port
microprocessors. The signals CS and CLK are generated
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