參數(shù)資料
型號(hào): LTC1297
廠商: Linear Technology Corporation
英文描述: Single Chip 12-Bit Data Acquisition Systems(5V,單片,12位數(shù)據(jù)采集系統(tǒng)(內(nèi)置采樣和保持))
中文描述: 單芯片12位數(shù)據(jù)采集系統(tǒng)(5V的,單片,12位數(shù)據(jù)采集系統(tǒng)(內(nèi)置采樣和保持))
文件頁(yè)數(shù): 10/24頁(yè)
文件大小: 398K
代理商: LTC1297
10
LTC1292/LTC1297
the MPU. The data is right-justified in the two memory
locations (Figure 2). This was made possible by delaying
the falling edge of CS till after the second CLK. ANDing the
first byte with 0F
HEX
clears the four most significant bits.
This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
U
S
A
O
PPLICATI
IU
U
LABEL MNEMONIC
LDAA
STAA
LDAA
STAA
LDAA
OPERAND
#$50
$1028
#$1B
$1009
#$00
COMMENTS
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DUMMY DIN WORD INTO
ACC A
LOAD DUMMY DIN DATA INTO $50
LOAD INDEX REGISTER X WITH
$1000
LOAD ACC B WITH $00
LOAD DUMMY DIN INTO ACC A
FROM $50
LOAD DUMMY DIN INTO SPI,
START SCK
DELAY CS FALL TIME TO RIGHT
JUSTIFY DATA
STAA
LDX
$50
#$1000
LOOP
LDAB
LDAA
#$00
$50
STAA
$102A
NOP
MC68HC11 CODE for LTC1292 Interface
STAB
$08, X
D0 GOES LOW (CS GOES LOW)
NOP
6 NOPS FOR TIMING
LDAA
LDAA
STAA
STAA
$1029
$102A
$61
$102A
CHECK SPI STATUS REG
LOAD LTC1292 MSBs INTO ACC A
STORE MSBs IN $61
LOAD DUMMY DIN INTO SPI,
START SCK
NOPS
6 NOPS FOR TIMING
BSET
LDAA
LDAA
STAA
$08,X,$01
$1029
$102A
$62
D0 GOES HIGH (CS GOES HIGH)
CHECK SPI STATUS REGISTER
LOAD LTC1292 LSBs IN ACC
STORE LSBs IN $62
JMP
LOOP
START NEXT CONVERSION
LABEL MNEMONIC
OPERAND
COMMENTS
BYTE 2
B3
B7
B6
B5
B4
B2
B0
B1
B10
B9
B8
B11
O
O
O
O
BYTE 1
D
OUT
FROM LTC1292 STORED ON MC68HC11 RAM
LOCATION #61
LOCATION #62
MSB
LTC1292/7 F02
CLK
D
OUT
LTC1292
CS
ANALOG
INPUTS
DO
SCK
MISO
MC68HC11
Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
Figure 3. Data Exchange Between LTC1297 and MC68HC11
For the LTC1297 (Figure 3) a delay must be introduced to
accommodate the setup time, t
suCS
, before the dummy
D
IN
word is sent to the data register. The first 8-bit transfer
clocks B11 through B6 of the A/D conversion result into
the processor. The second 8-bit transfer clocks the re-
maining bits B5 through B0 into the MPU. Note B1 and B2
from the LSB-first data word have also been clocked in.
CLK
CS
D
OUT
MPU
RECEIVED WORD
LTC1292/7 F03
B7
B6
B5
B4
B3
B2
B1
B0
B1
B8
B9
B10
B11
BYTE 2
B8
B7
B6
B9
B10
0
B11
1ST TRANSFER
2ND TRANSFER
BYTE 1
B0
B1
B2
B1
B2
B4
B5
B3
B2
B3
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