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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LTC1287CCN8 |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/16闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DATA ACQ SYS 12BIT 3V 8-DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 椤炲瀷锛� | 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 12 b |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 30k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 闆绘簮闆诲锛� | 3V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-PDIP |
| 鍖呰锛� | 绠′欢 |
LTC1287
11
1287fa
DOUT
CLK
B11
HI-Z
B10
LTC1287 F8c
CS
1ST BIT TEST (鈥�) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(鈥�) INPUT
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 9. Adequate Settling of Op Amp Driving Analog Input
(see Figures 8a, 8b and 8c). Again the 鈥�+鈥� and 鈥溾€撯€� input
sampling times can be extended as described above to
accommodate slower op amps. For single supply low
voltage application the LT1797 and LT1677 can be made
to settle well even with the minimum settling windows of
6
s (鈥�+鈥� input) and 2s (鈥溾€撯€� input) which occur at the
maximum clock rates (CLK = 500kHz). Figures 9 and 10
show examples of adequate and poor op amp settling. The
LT1077, LT1078 or LT1079 can be used here to reduce
power consumption. Placing an RC network at the output
of the op amps will inprove the settling response and also
reduce the broadband noise.
effectively 鈥渉eld鈥� by the sample and hold and will not affect
the conversion result. It is critical that the 鈥溾€撯€� input voltage
be free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing RSOURCE鈥� and C2 will
improve settling time. If large 鈥溾€撯€� input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 500kHz,
RSOURCE鈥� < 200 and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
HORIZONTAL: 500ns/DIV
Figure 8c. Setup Time (tSUCS) is Not Met
VERTICAL:
5mV/DIV
VERTICAL:
5mV/DIV
HORIZONTAL: 20
s/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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