DOUT CLK B11 HI-Z B9 B10 LTC1287 F8a CS 1ST BIT TEST (鈥�) INPUT MUST SETTLE DURING THI" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� LTC1287CCN8
寤犲晢锛� Linear Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 2/16闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC DATA ACQ SYS 12BIT 3V 8-DIP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 50
椤炲瀷锛� 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛�
鍒嗚鲸鐜囷紙浣嶏級锛� 12 b
閲囨ǎ鐜囷紙姣忕锛夛細 30k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛屽苟鑱�(li谩n)
闆诲闆绘簮锛� 鍠浕婧�
闆绘簮闆诲锛� 3V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 閫氬瓟
灏佽/澶栨锛� 8-DIP锛�0.300"锛�7.62mm锛�
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-PDIP
鍖呰锛� 绠′欢
10
LTC1287
1287fa
DOUT
CLK
B11
HI-Z
B9
B10
LTC1287 F8a
CS
1ST BIT TEST (鈥�) INPUT MUST
SETTLE DURING THIS TIME
tSUCS
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(鈥�) INPUT
DOUT
CLK
B11
HI-Z
B9
B10
LTC1287 F8b
CS
1ST BIT TEST (鈥�) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(鈥�) INPUT
鈥�+鈥� Input Settling
The input capacitor is switched onto the 鈥�+鈥� input during
the sample phase (tSMPL, see Figures 8a, 8b and 8c). The
sample period can be as short as tWHCS + 0.5 CLK cycle or
as long as tWHCS + 1.5 CLK cycles before a conversion
starts. This variability depends on where CS falls relative
to CLK. The voltage on the 鈥�+鈥� input must settle completely
within the sample period. Minimizing RSOURCE+ and C1
will improve the settling time. If large 鈥�+鈥� input source
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
resistance must be used, the sample time can be increased
by using a slower CLK frequency. With the minimum
possible sample time of 6.0
s, RSOURCE+ < 4.0k and C1
< 20pF will provide adequate settle time.
鈥溾€撯€� Input Settling
At the end of the sample phase the input capacitor switches
to the 鈥溾€撯€� input and the conversion starts (see Figures 8a,
8b and 8c). During the conversion, the 鈥�+鈥� input voltage is
鈥�+鈥� and 鈥溾€撯€� Input Settling Windows
Figure 8b. Setup Time (tSUCS) is Met
Figure 8a. Setup Time (tSUCS) is Met
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
LTC1287CCN8#PBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 3V 8-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
LTC1288CN8 鍔熻兘鎻忚堪:IC A/D CONV SAMPLING 12BIT 8-DIP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊�(g猫)鍠锛屽柈妤�
LTC1288CN8#PBF 鍔熻兘鎻忚堪:IC A/D CONV SAMPLING 12BIT 8-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:TSA1204 View All Specifications 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:20M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:155mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-TQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:48-TQFP锛�7x7锛� 鍖呰:Digi-Reel® 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:4 鍊�(g猫)鍠锛屽柈妤碉紱2 鍊�(g猫)宸垎锛屽柈妤� 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈�:1156 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:497-5435-6
LTC1288CN8PBF 鍒堕€犲晢:Linear Technology 鍔熻兘鎻忚堪:LTC1288CN8PBF
LTC1288CS8 鍔熻兘鎻忚堪:IC A/D CONV SAMPLING 12BIT 8SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊�(g猫)鍠锛屽柈妤�
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

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鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩�(g貌u)銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

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