參數(shù)資料
型號(hào): LSIFC909
英文描述: LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00
中文描述: LSIFC909光纖通道I / O處理器技術(shù)手冊(cè)2.1 8 / 00
文件頁(yè)數(shù): 60/144頁(yè)
文件大?。?/td> 1496K
代理商: LSIFC909
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5-4
Registers
5.3.1 Support for PCI Cache Line Size Register
The LSIFC909 supports the PCI specification for an 8-bit
Cache Line
Size
register in PCI configuration space; it can sense and react to
nonaligned addresses corresponding to cache line boundaries.
5.3.2 Selection of Cache Line Size
The cache logic will select a cache line size based on the value specified
in the
Cache Line Size
register.
Note:
If an illegal value is specified in the PCI
Cache Line Size
register (something other than 2, 4, 8, 16, 32, 64, or 128),
caching is disabled. Otherwise, the LSIFC909 uses this
value for all aligned burst data transfers.
5.3.3 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; i.e., the master intends to write all
bytes within the addressed cache line in a single PCI transaction, unless
interrupted by the target. This command requires implementation of the
PCI
Cache Line Size
register at address 0x0C in the PCI configuration
space.
5.3.3.1 Alignment
The LSIFC909 uses the calculated line size value to monitor the current
address for alignment to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by using a noncache
command.
For nonaligned initial addresses, the chip will execute a burst to bring the
address counter to an aligned value. Once a cache line boundary is
reached, the chip will use the cache line size as the burst size from then
on, except in the case of
Multiple Cache Line Transfers
. The alignment
process is finished at this point. Memory Write and Invalidate commands
are issued when the following conditions are met:
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