參數(shù)資料
型號: LSIFC909
英文描述: LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00
中文描述: LSIFC909光纖通道I / O處理器技術(shù)手冊2.1 8 / 00
文件頁數(shù): 58/144頁
文件大?。?/td> 1496K
代理商: LSIFC909
5-2
Registers
AD[10:8] are to be used for multifunction devices. The host processor
uses the PCI configuration space to initialize the LSIFC909.
At initialization time, each PCI device is assigned a base address for
memory accesses and I/O accesses. On every access, the LSIFC909
compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. A decode of
C_BE[7:0]/ determines which registers and what type of access is to be
performed.
5.2 PCI Bus Commands Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[7:0]/ lines
during the address phase. PCI bus command encoding and types appear
in
Table 5.1
.
The Memory Read, Memory Read Line, and Memory Read Multiple
commands read data from an agent mapped in memory address space.
The Memory Write, and Memory Write and Invalidate commands write
data to an agent when mapped in memory address space.
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