參數(shù)資料
型號: LPC3180FEL320
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface
封裝: LPC3180FEL320<SOT824-1 (LFBGA320)|<<http://www.nxp.com/packages/SOT824-1.html<1<Always Pb-free,;LPC3180FEL320/01<SOT824-1 (LFBGA320)|<<http://www.nxp.com/packages/SOT824-
文件頁數(shù): 26/36頁
文件大小: 763K
代理商: LPC3180FEL320
LPC3180_2
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 02 — 15 February 2007
26 of 36
NXP Semiconductors
LPC3180
16/32-bit ARM microcontroller with external memory interface
At the PLL output, there is a post-divider that can be used to bring the CCO frequency
down to the desired PLL output frequency. The post-divider value ‘P’, can divide the CCO
output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO
output to be used directly. The maximum PLL output frequency that is supported by the
CPU is 208 MHz.
6.24.3
Power control and modes
The LPC3180 supports three operational modes, two of which are specifically designed to
reduce power consumption. The modes are: Run mode, Direct Run mode, and Stop
mode.
Run mode is the normal operating mode for applications that require the CPU, AHB bus,
or any peripheral function other than the USB block to run faster than the main oscillator
frequency. In Run mode, the CPU can run at up to 208 MHz and the AHB bus can run at
up to 104 MHz.
Direct Run mode allows reducing the CPU and AHB bus rates in order to save power.
Direct Run mode can also be the normal operating mode for applications that do not
require the CPU, AHB bus, or any peripheral function other than the USB block to run
faster than the main oscillator frequency. Direct Run mode is the default mode following
chip reset.
Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals
other than the USB block.
6.24.4
APB bus
Many peripheral functions are accessed by on-chip APB busses that are attached to the
higher speed AHB bus. The APB bus performs reads and writes to peripheral registers in
three peripheral clocks.
6.24.5
FAB bus
Some peripherals are placed on a special bus called FAB that allows faster CPU access
to those peripheral functions. Write access to FAB peripherals takes a single AHB clock.
Read access to FAB peripherals takes two AHB clocks.
6.25 Emulation and debugging
The LPC3180 supports emulation and debugging via a dedicated JTAG serial port. An
Embedded Trace Buffer allows tracing program execution. The dedicated JTAG port
allows debugging of all chip features without impact to any pins that may be used in the
application.
6.25.1
EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the
Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
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