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參數(shù)資料
| 型號： | LPC3180FEL320 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 16-32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface |
| 封裝： | LPC3180FEL320<SOT824-1 (LFBGA320)|<<http://www.nxp.com/packages/SOT824-1.html<1<Always Pb-free,;LPC3180FEL320/01<SOT824-1 (LFBGA320)|<<http://www.nxp.com/packages/SOT824- |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 763K |
| 代理商： | LPC3180FEL320 |
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LPC3180_2
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 02 — 15 February 2007
21 of 36
NXP Semiconductors
LPC3180
16/32-bit ARM microcontroller with external memory interface
6.13.2.1
Features
Each high-speed UART has 64 byte Receive and Transmit FIFOs.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, 16 B, 32 B, and 48 B.
Transmitter FIFO trigger points at 0 B, 4 B, and 8 B.
Each high-speed UART has an internal baud rate generator.
The high-speed UARTs are designed to support data rates of (2400, 4800, 9600,
19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s.
Each UART includes an internal loopback mode.
6.14 I
2
C-bus serial I/O controller
There are two I
2
C-bus interfaces in the LPC3180. The blocks for the I
2
C-bus are a master
only implementation supporting the 400 kHz I
2
C-bus mode and lower rates, with 7-bit
slave addressing. Each has a four word FIFO for both transmit and receive. An interrupt
signal is available from each block.
6.14.1
Features
The two I
2
C-bus blocks are standard I
2
C-bus compliant interfaces that may be used in
Single Master mode only.
Programmable clock to allow adjustment of I
2
C-bus transfer rates.
Bidirectional data transfer.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
6.15 SPI serial I/O controller
The LPC3180 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire serial
interface that is able to interface with a large range of serial peripheral or memory devices
(SPI mode 0 to 3 compatible slave devices).
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3180 does not support operation as a slave.
6.15.1
Features
Supports slaves compatible with SPI modes 0 to 3.
Half duplex synchronous transfers.
DMA support for data transmit and receive.
1-bit to 16-bit word length.
Choice of LSB or MSB first data transmission.
64
×
16-bit input or output FIFO.
Bit rates up to 52 Mbit/s.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3180FEL320,551 | 功能描述:ARM微控制器 - MCU ARM9 FLTNG PNT CO-PR FLTNG POINT CO-PROC RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3180FEL320/01 | 制造商:NXP Semiconductors 功能描述:MCU 16-Bit/32-Bit LPC3100 ARM926EJ-S RISC ROMLess 1.2V/1.8V/3.3V 320-Pin LFBGA Tray |
| LPC3180FEL320/01,5 | 功能描述:ARM微控制器 - MCU ARM9 64KRAM VFP USB OTG BGA320 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3180FEL320/015 | 制造商:NXP Semiconductors 功能描述:MCU ARM9 320LFBGA |
| LPC3180FEL320551 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 208MHZ LFBGA-320 |
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