參數(shù)資料
型號(hào): LPC3180FEL320
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface
封裝: LPC3180FEL320<SOT824-1 (LFBGA320)|<<http://www.nxp.com/packages/SOT824-1.html<1<Always Pb-free,;LPC3180FEL320/01<SOT824-1 (LFBGA320)|<<http://www.nxp.com/packages/SOT824-
文件頁(yè)數(shù): 22/36頁(yè)
文件大?。?/td> 763K
代理商: LPC3180FEL320
LPC3180_2
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 02 — 15 February 2007
22 of 36
NXP Semiconductors
LPC3180
16/32-bit ARM microcontroller with external memory interface
Busy input function.
DMA time out interrupt to allow detection of end of reception when using DMA.
Timed interrupt to facilitate emptying the FIFO at the end of a transmission.
SPI clock and data pins may be used as general purpose pins if the SPI is not used.
6.16 SD card controller
The SD interface allows access to external SD memory cards. The SD card interface
conforms to the SD Memory Card Specification Version 1.01.
6.16.1
Features
Conformance to the SD Memory Card Specification Version 1.01.
DMA is supported through the system DMA controller.
Provides all functions specific to the SD memory card. These include the clock
generation unit, power management control, command and data transfer.
6.17 Keyboard scan
The keyboard scan function can automatically scan a keyboard of up to 64 keys in an
8
×
8 matrix. In operation, the keyboard scanner’s internal state machine will normally be
in an idle state, with all KEY_ROW[n] pins set high, waiting for a change in the column
inputs to indicate that one or more keys have been pressed.
When a keypress is detected, the matrix is scanned by setting one output pin high at a
time and reading the column inputs. After de-bouncing, the keypad state is stored and an
interrupt is generated. The keypad is then continuously scanned waiting for ‘extra key
pressed’ or ‘key released’. Any new keypad state is scanned and stored into the matrix
registers followed by a new interrupt request to the interrupt controller. It is possible to
detect and separate up to 64 multiple keys pressed.
6.17.1
Features
Supports up to 64 keys in 8
×
8 matrix.
Programmable debounce period.
A key press can wake up the CPU from Stop mode.
6.18 High-speed timer
The high-speed timer block is clocked by the main peripheral clock. The clock is first
divided down in a 16-bit programmable prescale counter which clocks a 32-bit
Timer/Counter.
The high-speed timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and cause the Timer/Counter to
either continue to run, stop, or be reset. The high-speed timer also includes two capture
registers that can take a snapshot of the Timer/Counter value when an input signal
transitions. A capture event may also generate an interrupt.
6.18.1
Features
32-bit Timer/Counter with programmable 16-bit prescaler.
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