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參數資料
| 型號： | LPC2470 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Flashless 16-bit/32-bit micro; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface |
| 中文描述： | 毛邊16-bit/32-bit微，以太網，CAN，液晶顯示器，USB 2.0設備/主機/ OTG功能，外部存儲器接口 |
| 文件頁數： | 46/72頁 |
| 文件大?。?/td> | 365K |
| 代理商： | LPC2470 |
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LPC2470_0
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 00.01 — 5 October 2007
46 of 72
NXP Semiconductors
LPC2470
Fast communication chip
The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if
this reset source is enabled in software) to inactivate the LPC2470 when the voltage on
the V
DD(3V3)
pins falls below 2.65 V. The BOD circuit maintains this reset down below 1 V,
at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
7.26.4
AHB
The LPC2470 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB
SRAM.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
7.26.5
External interrupt inputs
The LPC2470 includes up to 68 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
7.26.6
Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM, the SRAM, or external memory. This allows code running in different memory
spaces to have control of the interrupts.
When booting from an external memory the interrupt vectors are mapped to the bottom of
the external memory. Once booting is over the application must map interrupt vectors to
the proper domain.
7.27 Emulation and debugging
The LPC2470 support emulation and debugging via a JTAG serial port. A trace port allows
tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LPC2470_11 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, LCD, USB 2.0 device/host/OTG |
| LPC2470_1109 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface |
| LPC2470FBD208 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit micro; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface |
| LPC2470FBD208,551 | 功能描述:ARM微控制器 - MCU LCD CONT/ETHNET USB/HOST/OTG RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數據總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數據 RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC2470FET208 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit micro; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface |
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