參數(shù)資料
型號: LPC2377FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 512 kB flash with ISP-IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC-DAC
中文描述: 32-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 4/68頁
文件大?。?/td> 1443K
代理商: LPC2377FBD144
LPC2377_78
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 17 June 2010
4 of 68
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
5. Block diagram
(1) LPC2378 only.
Fig 1.
LPC2377/78 block diagram
power domain 2
LPC2377/78
A[15:0]
OE, CS0, CS1,
BLS0
D[7:0]
EXTERNAL
MEMORY
CONTROLLER
ALARM
002aac574
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
56 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
8
×
AD0
RTCX1
RTCX2
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
RD1, RD2
TD1, TD2
CAN1, CAN2
(1)
2
×
USB_D+/USB_D
2
×
USB_CONNECT
2
×
USB_UP_LED
XTAL1
TCK TDO
EXTIN0
XTAL2
TRST
TDI
TMS
HIGH-SPEED
GPI/O
104 PINS
TOTAL
32 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
SRAM
TEST/DEBUG
INTERFACE
E
T
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
V
DD(DCDC)(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
(1)
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2,
2
×
MAT0/MAT1/
MAT3
6
×
PWM1
2
×
PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
RMII(8)
RESET
V
BUS
DBGEN
P0, P2
AHB2
AHB1
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