參數(shù)資料
型號: LMX2531LQ1500EX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36
封裝: 6 X 6 MM, 0.8 MM, LCC-36
文件頁數(shù): 5/24頁
文件大?。?/td> 458K
代理商: LMX2531LQ1500EX
2.1 REGISTER R0
The action of programming the R0 register activates a frequency calibration routine for the VCO. This calibration is necessary to
get the VCO to center the tuning voltage for optimal performance. If the temperature drifts considerably, then the PLL should stay
in lock, provided that the temperature drift specification is not violated.
2.1.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator
The NUM word is split between the R0 register and R1 register. The Numerator bits determine the fractional numerator for the
delta sigma PLL. This value can go from 0 to 4095 when the FDM bit ( R3[22] ) is 0 (the other bits in this register are ignored), or
0 to 4194303 when the FDM bit is 1.
NUM[21:12]
NUM[11:0]
Fra
ctio
nal
Nu
mer
ator
0
...
409
503
1
409
6
0
1
0
...
419
430
3
1
Note that there are restrictions on the fractional numerator value depending on the R counter value if it is 16 or 32.
2.1.2 N[7:0] and N[10:8]
The N counter is 11 bits. 8 of these bits are located in the R0 register, and the remaining 3 (MSB bits) are located in the R1 register.
The LMX2531LQ1500E consists of an A, B, and C counter, which work in conjunction with the 16/17/20/21 prescaler in order to
form the final N counter value.
N[10:8]
N[7:0]
N Value
C
B
A
<55
Values less than 55 are prohibited.
55
0
1
0
1
...
2039
1
0
1
13
www.national.com
LMX2531LQ1500E
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