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參數(shù)資料
| 型號： | LMX2531LQ1500EX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.8 MM, LCC-36 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2531LQ1500EX |
1.0 Functional Description
The LMX2531LQ1500E is a low power, high performance
frequency synthesizer system which includes the PLL, VCO,
and partially integrated loop filter. Section 2.0 on program-
ming describes the bits mentioned in this section in more
detail.
1.1 REFERENCE OSCILLATOR INPUT
Because the VCO frequency calibration algorithm is based on
clocks from the OSCin pin, there are certain bits that need to
be
set
depending
on
the
OSCin
frequency.
XTLSEL ( R6[22:20] ) and XTLDIV ( R7[9:8] ) are both need
to be set based on the OSCin frequency.
1.2 R DIVIDER
The R divider divides the OSCin frequency down to the phase
detector frequency. The only valid R counter values are 1, 2,
4, 8, 16, and 32. The R divider also has an impact on the
fractional modulus that can be used, if it is greater than 8.
1.3 N DIVIDER AND FRACTIONAL CIRCUITRY
The N divider on the LMX2531LQ1500E is fractional and can
achieve
any
fractional
denominator
between
1
and
4,194,303. The integer portion of the N counter value, N
Inte-
ger, is determined by the value of the N word. Because there
is a 16/17/20/21 prescaler, there are restrictions on how small
the N
Integer value can be. This is because this value is actually
formed by several different prescalers in the quadruple mod-
ulus prescaler in order to achieve the desired value. The
fractional word, N
Fractional , is a fraction formed with the NUM
and DEN words. The fractional denominator value, DEN, can
be set from 2 to 4,194,303. The case of DEN=0 makes no
sense, since this would cause an infinite N value, and the case
of 1 makes no sense (but could be done), because integer
mode should be used in these applications. All other values
in this range, like 10, 32,734, or 4,000,000 are all valid. Once
the fractional denominator, DEN, is determined, the fractional
numerator, NUM, is intended to be varied from 0 to DEN-1.
Sometimes, expressing the same fraction, like 1/10, in terms
of larger fractions, like 100/10000, sometimes yields better
fractional spurs, but other times it does not. This can be im-
pacted by the fractional modulator order and the dithering
mode selected, as well as the loop bandwidth, and other ap-
plication specific criteria. So in general, the total N counter
value is determined by:
N = N
Integer + NFractional
In order to calculate the minimum necessary fractional de-
nominator, the R counter value needs to be chosen, so that
the comparison frequency is known. The minimum necessary
fractional denominator can be calculated by dividing the com-
parison frequency by the greatest common multiple of the
comparison frequency and the OSCin frequency. For exam-
ple, consider the case of a 10 MHz crystal and a 200 kHz
channel spacing. If the R counter value is chosen to be 2, then
the comparison frequency will be 5 MHz. The greatest com-
mon multiple of 200 kHz and 5 MHz is 200 kHz. If one takes
5 MHz divided by 200 kHz, this is 25. So a fractional denom-
inator of 25, or any multiple of 25 would work in this situation.
Now consider a second example where the channel spacing
is changed to 30 kHz. If it is again assumed that the compar-
ison frequency is 5 MHz, then the greatest common multiple
of 30 kHz and 5 MHz is 10 kHz. 5 MHz divided by 10 kHz is
500. In this situation, a fractional denominator of 500, or any
multiple of 500 would suffice. For a final example, consider
an application with a fixed output frequency of 2110.8 MHz
and a crystal frequency of 19.68 MHz. If the R counter is cho-
sen to be 2, then the comparison frequency is 9.84 MHz. The
greatest common multiple of 9.84 MHz and 2110.8 MHz is
240 kHz. 9.84 MHz / 240 kHz = 41. So the fractional denom-
inator could be 41, or any multiple of 41. For this last example
value, the entire N counter value would be 214 + 21/41.
The fractional value is achieved with a delta sigma architec-
ture. In this architecture, an integer N counter is modulated
between different values in order to achieve a fractional value.
On this part, the modulator order can be zero (integer mode),
two, three, or four. The higher the fractional modulator order
is, the lower the spurs theoretically are. However, this is not
always the case, and the higher order fractional modulator
can sometimes give rise to additional spurious tones, but this
is dependent on the application. This is why it is an advantage
to have the modulator order selectable. Dithering also has an
impact on the fractional spurs, but a lesser one.
1.4 PHASE DETECTOR
The phase detector compares the outputs of the R and N
counters and puts out a correction current corresponding to
the phase error. The choice of the phase detector frequency
does have an impact on performance. When determining
which phase detector frequency to use, the restrictions on the
R counter values must be taken into consideration.
1.5 PARTIALLY INTEGRATED LOOP FILTER
The LMX2531LQ1500E integrates the third pole (formed by
R3 and C3) and fourth pole (formed by R4 and C4) of the loop
filter. This loop filter can be enabled or bypassed using the
EN_LPFLTR ( R6[15] ). The values for C3, C4, R3, and R4
can also be programmed independently through the MI-
CROWIRE interface . Also, the values for R3 and R4 can be
changed during FastLock, for minimum lock time. It is recom-
mended that the integrated loop filter be set to the maximum
possible attenuation (R3=R4=40k
Ω, C3=C4=100pF), the in-
ternal loop filter is more effective at reducing certain spurs
than the external loop filter. However, if the attenuation of the
internal loop filter is too high, it limits the maximum attainable
loop bandwidth that can be achieved, which corresponds to
the case where the shunt loop filter capacitor, C1, is zero.
Increasing the charge pump current and/or the comparison
frequency increases the maximum attainable loop bandwidth
when designing with the integrated filter. Furthermore, this
often allows the loop filter to be better optimized and have
stronger attenuation. If the charge pump current and com-
parison frequency are already as high as they go, and the
maximum attainable loop bandwidth is still too low, the resis-
tor and capacitor values can be decreased or the internal loop
filter can even be bypassed. Note that when the internal loop
filter is bypassed, there is still a small amount of input capac-
itance on front of the VCO on the order of 200 pF. For design
tools and more information on partially integrated loop filters,
go to wireless.national.com.
1.6 LOW NOISE, FULLY INTEGRATED VCO
The LMX2531LQ1500E includes a fully integrated VCO, in-
cluding the inductors. In order for optimum phase noise per-
formance, this VCO has frequency and phase noise calibra-
tion algorithms. The frequency calibration algorithm is
necessary because the VCO internally divides up the fre-
quency range into several bands, in order to achieve a lower
tuning gain, and therefore better phase noise performance.
The frequency calibration routine is activated any time that
the R0 register is programmed. If the temperature shifts con-
siderably and the R0 register is not programmed, then it can
not drift more than the maximum allowable drift for continuous
lock,
ΔT
CL, or else the VCO is not guaranteed to stay in lock.
www.national.com
8
LMX2531LQ1500E
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