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參數(shù)資料
| 型號(hào)： | LMX2531LQ1500EX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.8 MM, LCC-36 |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2531LQ1500EX |
The phase noise calibration algorithm is necessary in order
to
achieve
the
lowest
possible
phase
noise.
The
VCO_ACI_SEL bit ( R6[19:16] ) needs to be set to the correct
value to ensure the best possible phase noise.
The gain of the VCO can change considerably over frequen-
cy. It is lowest at the minimum frequency and highest at the
maximum frequency. This range is specified in the datasheet.
When designing the loop filter, the following method is rec-
ommended. First, take the geometric mean of the minimum
and maximum frequencies that are to be used. Then use a
linear approximation to extrapolate the VCO gain.
1.7 PROGRAMMABLE DIVIDE BY 2
All options of the LMX2531LQ1500E offer a divide by 2 option.
This allows the user to get exactly half of the VCO frequency,
by dividing the output of the VCO output by two. Because this
divide by two is outside feedback path between the VCO and
the PLL, the loop filter and counter values are set up for the
VCO frequency before it is divide by two. Note that R0 register
should be reprogrammed the first time after the DIV2 bit is
enabled or disabled for optimal phase noise performance.
1.8 CHOOSING THE CHARGE PUMP CURRENT AND
COMPARISON FREQUENCY
The LMX2531LQ1500E has 16 levels of charge pump cur-
rents and a highly flexible fractional modulus. This gives the
user many degrees of freedom. This section discusses some
of the design considerations. From the perspective of the PLL
noise, choosing the charge pump current and comparison
frequency as high as possible are best for optimal phase
noise performance. The far out PLL noise improves 3 dB for
every doubling of the comparison frequency, but at lower off-
sets, this effect is much less due to the PLL 1/f noise. In-
creasing the charge pump current improves the phase noise
about 3 dB per doubling of the charge pump current, although
there are small diminishing returns as the charge pump cur-
rent goes higher.
From a loop filter design and PLL phase noise perspective,
one might think to always design with the highest possible
comparison frequency and charge pump current. However, if
one considers the worst case fractional spurs that occur at an
output frequency equal to 1 channel spacing away from a
multiple of the OSCin frequency, then this gives reason to re-
consider. If the comparison frequency or charge pump cur-
rents are too high, then these spurs could be degraded, and
the loop filter may not be able to filter these spurs as well as
theoretically predicted. For optimal spur performance, a com-
parison frequency in the ballpark of 2.5 MHz and a charge
pump current of 1X are recommended.
9
www.national.com
LMX2531LQ1500E
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2531LQ1515E | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 1450MHz to 1580MHz 36-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:CLOCK SYNTHESIZER 1.6GHZ 36LLP |
| LMX2531LQ1515E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2531LQ1570E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum High Performance Frequency Synthesizer System with Integrated VCO |
| LMX2531LQ1570E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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