參數(shù)資料
型號(hào): LMX2335UTM/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO16
封裝: PLASTIC, TSSOP-16
文件頁數(shù): 24/48頁
文件大?。?/td> 3127K
代理商: LMX2335UTM/NOPB
Test Setups (Continued)
LMX2335U and LMX2336U OSC
in Sensitivity Test Setup
10136741
The block diagram above illustrates the setup required to
measure the LMX2336U device’s OSC
in buffer sensitivity
level. The same setup is used for the LMX2336TMEB/
LMX2336SLEEB Evaluation Boards. This setup is similar to
the f
IN sensitivity setup except that the signal generator is
now connected to the OSC
in pin and both fIN pins are tied to
V
CC. The 51
shunt resistor matches the OSC
in input to the
signal generator. The R counter is typically set to 1000, i.e.
RF1 R_CNTR Word = 1000 or RF2 R_CNTR Word = 1000.
The reference divider output is routed to the F
oLD pin by
selecting the RF1 PLL R Divider Output word (F
oLD Word
= 2 or 10) or the RF2 PLL R Divider Output word (F
oLD
Word = 1 or 9) in Code Loader. Similarly, a Universal
Counter is connected to the F
oLD pin and is tied to the 10
MHz reference output from the signal generator. The output
of the reference divider is monitored and should be equal to
OSC
in/ RF1 R_CNTR or OSCin/ RF2 R_CNTR.
Again, V
CC is swept from 2.7V to 5.5V. The OSCin input
frequency and voltage level are then swept with the signal
generator. The measurements are repeated at different tem-
peratures, namely T
A = -40C, +25C, and +85C. Sensitivity
is reached when the frequency error of the divided input
signal is greater than or equal to 1 Hz.
The LMX2335U OSC
in sensitivity test setup is very much
similar to the above test setup.
LMX2335U/LMX2336U
www.national.com
30
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