- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄44573 > LMX2323TMX (NATIONAL SEMICONDUCTOR CORP) PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 PDF資料下載
參數(shù)資料
| 型號(hào)： | LMX2323TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 147K |
| 代理商： | LMX2323TMX |
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The MICROWIRE interface is comprised of an 18-bit shift register, a R register and a N register. The shift register consists of a
17-bit DATA field and a 1-bit address (ADDR) field as shown below. When Latch Enable transitions HIGH, data stored in the shift
register is loaded into either the R or N register depending on the ADDR bit as described in Table 2.1.1. The data is loaded MSB
first. The DATA field assignment for the R and N registers are shown in Table 2.1.2 below.
MSB
LSB
DATA [16:0]
ADDR
17
1
0
2.1.1 Address Bit Truth Table
When LE is transitioned high, data is transferred from the 18-bit shift register into either the 14-bit R register, or the 17-bit N reg-
ister depending upon the state of the ADDR bit.
ADDR
DATA Location
0
N register
1
R register
2.1.2 Register Content Truth Table
MSB
SHIFT REGISTER BIT LOCATION
LSB
17
16
15
14
13
12
11
10
9
8
7654
3
2
1
0
N Register
NB_CNTR
NA_CNTR
CTL_WORD
0
R Register
X
LD_OUT
PD_POL
CP_TRI
R_CNTR
1
2.2 R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R reg-
ister. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using the
bits R_CNTR as shown in
2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter). The ratio must be
≥ 2. The PD_POL
and CP_TRI bits control the phase detector polarity and charge pump TRI-STATE respectively, as shown in
2.2.2 R[11], R[12]
Truth Table. X denotes a don’t care condition.
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10987654
3210
X
LD_OUT
PD_POL
CP_TRI
R_CNTR [9:0]
1
2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter)
R_CNTR
Divide Ratio
9876543210
2
0000000010
3
0000000011
1,023
1111111111
Note: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited).
R_CNTR — These bits select the divide ratio of the programmable reference dividers.
2.2.2 R[11], R[12] Truth Table
Bit
Location
Function
0
1
CP_TRI
R[11]
Charge Pump TRI-STATE
Normal Operation
TRI-STATE
PD_POL
R[12]
Phase Detector Polarity
Negative
Positive
Note: Depending upon VCO characteristics, R[12] shoud be set accordingly. When VCO characteristics are positive, R[12] should be set HIGH. When VCO char-
acteristics are negative, R[12] should be set LOW.
LMX2323
www.national.com
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2323TM | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| LMX2330ATMX | PHASE LOCKED LOOP, 2500 MHz, PDSO20 |
| LMX2330LTMX/NOPB | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| LMX2330LMWC | PLL FREQUENCY SYNTHESIZER, 2500 MHz, UUC |
| LMX2330LMDC | PLL FREQUENCY SYNTHESIZER, 2500 MHz, UUC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2324 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| LMX2324A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LMX2324ASLBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|BICMOS|LLCC|16PIN|PLASTIC |
| LMX2324ATM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|BICMOS|TSSOP|16PIN|PLASTIC |
| LMX2324ATMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum? 2.2 GHz Frequency Synthesizer for RF Personal Communications (SL163188) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。