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參數(shù)資料
| 型號： | LMX2323TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 147K |
| 代理商： | LMX2323TMX |
Connection Diagram
Pin Descriptions
Pin No.
Pin
Name
I/O
Description
1
OSC
IN
I
Oscillator input. A CMOS inverting gate input. The input has a V
CC/2 input threshold
and can be driven from an external CMOS or TTL logic gate.
3V
P
—
Power supply for charge pump. Must be
≥ V
CC.
4V
CC
—
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane.
5CP
o
O
Internal charge pump output. For connection to a loop filter for driving the voltage
control input of an external oscillator.
6
GND
—
Ground.
7f
INB
I
RF prescaler complimentary input. In single-ended mode, a bypass capacitor should
be placed as close as possible to this pin and be connected directly to the ground
plane. The LMX2323 can be driven differentially when a bypass capacitor is omitted.
8f
IN
I
RF prescaler input. Small signal input from the voltage controlled oscillator.
9
Clock
I
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the
various counters and registers.
10
Data
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance
CMOS input.
11
LE
I
Load Enable input. When Load Enable transitions HIGH, data is loaded into either the
N or R register (control bit dependent). See timing diagram.
12
CE
I
PLL Enable. A LOW on CE powers down the device asynchronously and
TRI-STATEs the charge pump output.
14
LD
O
Lock detect output. This pin can be programmed to provide R counter output, N
counter output, digital lock detect (CMOS logic) or analog lock detect (open drain).
2, 13,
15, 16
NC
No Connect.
DS101362-2
Top View
Order Number LMX2323TM, LMX2323TMX
See NS Package Number MTC16
LMX2323
www.national.com
2
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