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參數(shù)資料
| 型號： | LMX2323 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum? 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinum？ 2.0千兆赫頻率合成射頻個人通信 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 185K |
| 代理商： | LMX2323 |
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The MICROWIRE interface is comprised of an 18-bit shift register, a R register and a N register. The shift register consists of a
17-bit DATA field and a 1-bit address (ADDR) field as shown below. When Latch Enable transitions HIGH, data stored in the shift
register is loaded into either the R or N register depending on the ADDR bit as described in Table 2.1.1. The data is loaded MSB
first. The DATA field assignment for the R and N registers are shown in Table 2.1.2 below.
MSB
LSB
DATA [16:0]
ADDR
17
1
0
2.1.1 Address Bit Truth Table
When LE is transitioned high, data is transferred from the 18-bit shift register into either the 14-bit R register, or the 17-bit N
register depending upon the state of the ADDR bit.
ADDR
0
1
DATA Location
N register
R register
2.1.2 Register Content Truth Table
MSB
17
SHIFT REGISTER BIT LOCATION
11
10
LSB
16
15
14
13
12
9
8
7
6
5
4
3
2
CTL_WORD
1
0
0
1
N Register
R Register
NB_CNTR
PD_POL
NA_CNTR
R_CNTR
X
X
LD_OUT
CP_TRI
2.2 R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R
register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using
the bits R_CNTR as shown in 2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter) The ratio must be
≥
2. The
PD_POL and CP_TRI bits control the phase detector polarity and charge pump TRI-STATE respectively, as shown in 2.2.2 R[11],
R[12] Truth Table X denotes a don’t care condition.
First Bit
17
X
SHIFT REGISTER BIT LOCATION
11
10
CP_TRI
Last Bit
1
16
X
15
14
13
12
9
8
7
6
5
4
3
2
0
1
LD_OUT
PD_POL
R_CNTR [9:0]
2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter)
R_CNTR
Divide Ratio
2
3
1,023
9
0
0
1
8
0
0
1
7
0
0
1
6
0
0
1
5
0
0
1
4
0
0
1
3
0
0
1
2
0
0
1
1
1
1
1
0
0
1
1
Note:
Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited).
R_CNTR—These bits select the divide ratio of the programmable reference dividers.
2.2.2 R[11], R[12] Truth Table
Bit
Location
R[11]
R[12]
Function
0
1
CP_TRI
PD_POL
Charge Pump TRI-STATE
Phase Detector Polarity
Normal Operation
Negative
TRI-STATE
Positive
Note:
Depending upon VCO characteristics, R[12] shoud be set accordingly. When VCO characteristics are positive, R[12] should be set HIGH. When VCO
characteristics are negative, R[12] should be set LOW.
L
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