參數(shù)資料
型號(hào): LMX2323
廠商: National Semiconductor Corporation
英文描述: PLLatinum? 2.0 GHz Frequency Synthesizer for RF Personal Communications
中文描述: PLLatinum? 2.0千兆赫頻率合成射頻個(gè)人通信
文件頁數(shù): 2/12頁
文件大?。?/td> 185K
代理商: LMX2323
Connection Diagram
Pin Descriptions
Pin No.
Pin
Name
OSC
IN
I/O
Description
1
I
Oscillator input. A CMOS inverting gate input. The input has a V
CC
/2 input threshold
and can be driven from an external CMOS or TTL logic gate.
Power supply for charge pump. Must be
V
CC
.
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Internal charge pump output. For connection to a loop filter for driving the voltage
control input of an external oscillator.
Ground.
RF prescaler complimentary input. In single-ended mode, a bypass capacitor should
be placed as close as possible to this pin and be connected directly to the ground
plane. The LMX2323 can be driven differentially when a bypass capacitor is omitted.
RF prescaler input. Small signal input from the voltage controlled oscillator.
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the
various counters and registers.
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance
CMOS input.
Load Enable input. When Load Enable transitions HIGH, data is loaded into either the
N or R register (control bit dependent). See timing diagram.
PLL Enable. A LOW on CE powers down the device asynchronously and
TRI-STATE
s the charge pump output.
Lock detect output. This pin can be programmed to provide R counter output, N
counter output, digital lock detect (CMOS logic) or analog lock detect (open drain).
No Connect.
3
4
V
P
V
CC
5
CP
o
O
6
7
GND
f
INB
I
8
9
f
IN
I
I
Clock
10
Data
I
11
LE
I
12
CE
I
14
LD
O
2, 13,
15, 16
NC
DS101362-2
Top View
Order Number LMX2323TM, LMX2323TMX
See NS Package Number MTC16
L
www.national.com
2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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