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參數(shù)資料
| 型號： | LM9801 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 中文描述： | Greyscale/24-Bit彩色線陣CCD傳感器處理器 |
| 文件頁數(shù)： | 31/34頁 |
| 文件大小： | 520K |
| 代理商： | LM9801 |
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Applications Information
(Continued)
Suggested timing for CIS devices is:
Mode
e
0 (Standard Mode)
*
RS Pulse Width
e
0 (2 MCLKs)
RS Pulse Polarity
e
0 (or 1 if circuit of Figure 21 is
used)
*
RS Pulse Position
e
0
Sample Reference Position
e
2
Sample Signal Position
e
14
w
1/
w
2/RS/TR Enable
e
0/0/1/1
TR Pulse Width
e
0
TR-
w
1 Guardband
e
0
TR Polarity
e
1
*
Signal Polarity
e
0
Dummy Pixels
e
2
Optical Black Pixels
e
10
(
*
Value given in CCD datasheet)
As CIS sensors approach pixel rates of 1 MHz and above
(corresponding to MCLK frequencies of 8 MHz and above),
the voltage during the reset level becomes less stable, mak-
ing it difficult to perform CDS on the output(Figure 22). The
solution is to create the ground reference externally, short-
ing the LM9801’s input to ground for half of the time using
the
w
1 clock, as shown in Figure 23.
TL/H/12814–49
FIGURE 22. High Speed CIS Waveforms
TL/H/12814–50
FIGURE 23. High Speed CIS Interface
10.0 HINTS AND COMMON SYSTEM DESIGN
PROBLEMS
10.1 Reading and Writing to the Configuration Register
The Configuration Register sends and receives data LSB
(Least Significant Byte) first. Some microcontrollers send
out data MSB (Most Significant Byte) first. The order of the
bits must be reversed to when using these microcontrollers.
Note:
Unlike the LM9800, the SYNC pin does not have to be held high to
send or receive data to or from the Configuration Register.
10.2 Setting the Dummy and Optical Black Pixel
Registers
The minimum value in the Dummy Pixels register is 2 (a
value of 0 or 1 will cause errors in the EOC and CCLK tim-
ing). Note that the value in this register should be equal to 1
plus the actual number of dummy pixels in the CCD. For
example, if the CCD being used with the LM9801 has 12
dummy pixels, this register should be set to 13. The mini-
mum number in the Optical Black Pixels register is 1.
10.3 Stretching the TR-
w
1 Guardband
Some CCDs (Sony’s ILX514, ILX518, and ILX524, for exam-
ple) require a TR to
w
1 guardband greater than the 100 ns
(2 MCLKs) provided by the LM9801. The circuit shown in
Figure 24 produces a 1
m
s
w
ROG (transfer) pulse with a
guardband between the end of the
w
ROG pulse and the
next edge of
w
1. This is done by setting the LM9801’s TR
pulse width register to 2
m
s and using the 74HC4538 to
generate a 1
m
s pulse inside that TR period to send to the
CCD.
TL/H/12814–51
FIGURE 24. Stretching the TR-
w
1 Guardband
http://www.national.com
31
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