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參數資料
| 型號： | LM9801 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 中文描述： | Greyscale/24-Bit彩色線陣CCD傳感器處理器 |
| 文件頁數： | 21/34頁 |
| 文件大?。?/td> | 520K |
| 代理商： | LM9801 |
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Applications Information
(Continued)
The Configuration Register is programmed by sending a
control byte to the serial port. This byte indicates whether
this is a read or a write operation, and gives the 3-bit ad-
dress of the register bank to be read from or written to. If
this is a read operation, the next 8 SCLKs will output the
data at the requested location on the SDO pin. If this is a
write operation, the data to be sent to the specified location
should be clocked in on the SDI input during the next 8
SCLKs. Data is sent and received using the LSB (Least Sig-
nificant Bit) first format.
For maximum system reliability, each configuration register
location can be read back and verified after a write.
If the serial I/O to the configuration register falls out of sync
for any reason, it can be reset by sending 8 or more SCLKs
with CS held high.
2.2 Writing Correction Coefficient Data on the
CD0–CD7 Bus
Correction coefficient data for each pixel is latched on the
rising edge of the CCLK output signal (see Diagram 10).
Note that there is a 3 pixel latency between when the coeffi-
cient data is latched and when the output data is available.
As Diagram 2,Pixel Pipeline Timing Overview shows, coeffi-
cient data for pixel n is latched shortly before the output
data for pixel n-2 becomes available on the output databus
(DD0–DD7). Note that there is no way to provide a correc-
tion coefficient for pixel 1, the first pixel in the CCD array.
This is not a problem since the first several pixels of the
CCD are used for clamping.
2.3 Reading Output Data on the DD0–DD7 Bus
The corrected digital output data representing each pixel is
available on the DD0–DD7 databus. The data is valid after
the falling edge of the EOC output. The RD input takes the
databus in and out of TRI-STATE. RD can be held low at all
times if there are no other devices needing the bus, or it can
be used to TRI-STATE the bus between pixels, allowing oth-
er devices access to the bus. Diagram 12,Data Timing (Out-
put and Coefficient Data Sharing Same Bus), shows how
EOC can be tied to RD to automatically multiplex between
coefficient data and conversion data.
2.4 MCLK
This is the master clock input that controls the LM9801. The
pixel conversion rate is fixed at 1/8 of this frequency. Many
of the timing parameters are also relative to the frequency
of this clock.
2.5 SYNC
This input signals the beginning of a line. When SYNC goes
high, the LM9801 generates a TR pulse, then begins con-
verting pixels until the SYNC line is brought low again. Since
there is no pixel counter in the LM9801, it will work with
CCDs of any length.
3.0 DIGITAL CCD INTERFACE
3.1 Buffering
w
1,
w
2, RS, and TR
The LM9801 can drive the
w
1,
w
2, RS, and TR inputs of
many CCDs directly, without the need for external buffers
between the LM9801 and the CCD. Most linear CCDs de-
signed for scanner applications require 0V to 5V signal
swings into 20 pF to 500 pF input loading. Series resistors
are typically inserted between the driver and the CCD to
control slew rate and isolate the driver from the large load
capacitances. The values of these resistors are usually giv-
en in the CCD’s datasheet.
4.0 ANALOG INTERFACE
4.1 Voltage Reference
The
1.225V
g
2% reference voltage capable of sinking between
2 mA and 5 mA of current coming from the 500
X
–1400
X
resistor string between REF OUT
HI
and REF IN. The
LM4041-1.2 1.225V bandgap reference is recommended for
this application as shown in Figure 2. The inexpensive ‘‘E’’
grade meets all the requirements of the application and is
available in a TO-92 (LM4041EIZ-1.2) package as well as a
SOT-23 package (LM4041EIM3-1.2) to minimize board
space.
two
REF
IN
pins
should
be
connected
to
a
Due to the transient currents generated by the LM9801’s
ADC, PGA, and CDS circuitry, the REF IN pins, the REF
OUT
MID
pin and the REF OUT
HI
pin should all be bypassed
to AGND with 0.1
m
F monolithic capacitors.
TL/H/12814-29
FIGURE 2. Voltage Reference Generation
4.2 Clamp Capacitor Selection
This section is very long because it is relatively complicated
to explain, but the answer is short and simple: A clamp ca-
pacitor value of 0.01
m
F should work in almost all applica-
tions. The rest of this section describes exactly how this
value is selected.
TL/H/12814–30
FIGURE 3. OS Clamp Capacitor and Internal Clamp
The output signal of many CCDs rides on a large DC offset
(typically 8V to 10V) which is incompatible with the
LM9801’s 5V operation. To eliminate this offset without re-
sorting to additional higher voltage components, the output
http://www.national.com
21
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