參數(shù)資料
型號： LM9627
廠商： National Semiconductor Corporation
英文描述： Metal Foil Resistor; Series:SMR1D; Resistance:2.5kohm; Resistance Tolerance:+/- 0.01 %; Power Rating:0.25W; Temperature Coefficient:+/-0.6 ppm; Terminal Type:PCB Surface Mount; Leaded Process Compatible:No
中文描述： 彩色CMOS圖像傳感器顯卡30醫(yī)科
文件頁數(shù)： 26/37頁
文件大?。?/td> 370K
代理商： LM9627
Confidential
26
www.national.com
Register Set
(continued)
Register Name Hclk Generator Register
Address
05 Hex
Mnemonic
VCLKGEN
Type
Read/Write
Reset Value
04 Hex.
Register Name Digital Video Mode 0
Address
06 Hex
Mnemonic
VMODE0
Type
Read/Write
Reset Value
00 Hex
Register Name Digital Video Mode 1
Address
07 Hex
Mnemonic
VMODE1
Type
Read/Write
Reset Value
00 Hext
Bit
Bit Symbol
7
PixClkMode
Register Name Digital Video Mode 2
Address
08 Hex
Mnemonic
VMODE2
Type
Read/Write
Reset Value
00 Hex
Bit
Bit Symbol
Description
7:0
HclkGen
Use to divide the frequency of
the sensors master clock input,
mclk
to generate the internal
sensor clock,
Hclk.
Program 00 Hex (the default) for
Hclk
to equal
mclk
or divide
mclk
by any number between 1
and FF Hex.
Bit
Bit Symbol
Description
7:6
PixDataSel
Use to program the number of
active bits on the digital video bus
d[11:0]
, starting from the MSB
(
d[11]
). Inactive bits are tri-stated.:
5:4
PixDataMsb
Use to program the routing of the
MSB output of the internal video
A/D to a bit on the digital video
bus.
3:0
Reserved
00
12 bit mode, bits
d[11:0]
of the digital
video bus are active.
This is the default.
01
10 bit mode, bits
d[11:2]
of the digital
video bus are active.
10
8 bit mode, bits
d[11:4]
of the digital
video bus are active.
11
Reserved.
00
A/D [11:0] -> d[11:0].
01
10
A/D [10:0] -> d[11:1]
A/D [9:0] -> d[11:2]
11
A/D [8:0] -> d[11:3]
Description
Assert to set the
pclk
to “data
ready mode”. Clear, the default, to
set
pclk
to “
free running mode
”.
Assert to set the
vsync
pin to
“pulse mode”. Clear (the default)
to set the
vsync
signal to “l(fā)evel
mode”.
Assert to force the
hsync
signal to
pulse for a minimum of four pixel
clocks at the end of each row.
Clear (the default) to force the
hsync
signal to a level indicating
valid data within a row.
Assert to set the active edge of
the pixel clock to negative. Clear
(the default) to set the active edge
of the clock to positive.
Assert to force the
vsync
signal to
generate a logic 0 during a frame
readout
(Level Mode),
or a nega-
tive pulse at the end of a frame
readout
(Pulse Mode)
. Clear (the
default) to force the
vsync
signal
to generate a logic 1 during a
frame readout
(Level Mode),
or a
negative pulse at the end of a
frame
readout
(Pulse Mode)
.
Assert to force the
hsync
signal to
generate a logic 0 during a row
readout
(Level Mode),
or a nega-
tive pulse at the end of a row
readout
(Pulse Mode)
. Clear (the
default) to force the
hsync
signal
to generate a logic 1 during a row
readout
(Level Mode),
or a nega-
tive pulse at the end of a readout
(Pulse Mode)
.
Assert to force the
vsync
pin to act
as an odd/even field indicator.
Clear (the default) to force the
vsync
pin to act as a vertical syn-
chronization signal.
Assert to tri-state all output signals
(data and control) on the digital
video port. Clear (default) to
enable all signals (data and con-
trol) on the digital video port.
6
VsyncMode
5
HsyncMode
4
PixClkPol
3
VsynPol
2
HsynPol
1
OddEvenEn
0
TriState
Bit
Bit Symbol
Description
7:4
HsyncAdjust
Use to program the leading edge
of
hsync
to the first valid pixel at
the beginning of each row. This
can be 0-hex to F-hex corre-
sponding to 0 - 15 pixel clocks.
Default 0.
Reserved
3:0
L
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