參數(shù)資料
型號： LM9627
廠商： National Semiconductor Corporation
英文描述： Metal Foil Resistor; Series:SMR1D; Resistance:2.5kohm; Resistance Tolerance:+/- 0.01 %; Power Rating:0.25W; Temperature Coefficient:+/-0.6 ppm; Terminal Type:PCB Surface Mount; Leaded Process Compatible:No
中文描述： 彩色CMOS圖像傳感器顯卡30醫(yī)科
文件頁數(shù)： 19/37頁
文件大?。?/td> 370K
代理商： LM9627
Confidential
19
www.national.com
Functional Description
(continued)
13.0 SERIAL BUS
The serial bus interface consists of the
sda
(serial data),
sclk
(serial clock) and
sadr
(device address select) pins. The
LM9627 can operate only as a slave.
The
sclk
pin is an input, it only and controls the serial interface,
all other clock functions within LM9627 use the master clock pin,
mclk
.
13.1
The serial bus will recognize a logic 1 to logic 0 transition on the
sda
pin while the
sclk
pin is at logic 1 as the
start
condition. A
logic 0 to logic 1 transition on the
sda
pin while the
sclk
pin is at
logic 1 is interrupted as the
stop
condition as shown in Figure
27.
Start/Stop Conditions
Figure 27. Start/Stop Conditions
13.2
The serial bus
Device Address
of the LM9627 is set to 1010101
when
sadr
is tied low and 0110011 when
sadr
is tied high. The
value for s
adr is
set at power up.
Device Address
13.3
The LM9627 will hold the value of the
sda
pin to a logic 0 during
the logic 1 state of the
Acknowledge
clock pulse on
sclk
as
shown in Figure 28.
Acknowledgment
Figure 28. Acknowledge
13.4
The master must ensure that data is stable during the logic 1
state of the
sclk
pin. All transitions on the
sda
pin can only occur
when the logic level on the sclk pin is “0” as shown in Figure 29.
Data Valid
Figure 29. Data Validity
13.5
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an
Acknowledge
. The most significant bit of
the byte is should always be transmitted first. See Figure 30.
Byte Format
13.6
A write operation is initiated by the master with a
Start Condition
followed by the sensor’s
Device Address
and
Write
bit. When
the master receives an
Acknowledge
from the sensor it can
transmit 8 bit internal register address. The sensor will respond
with a second
Acknowledge
signaling the master to transmit 8
write data bits. A third
Acknowledge
is issued by the sensor
when the data has been successfully received.
Write Operation
The write operation is completed when the master asserts a
Stop Condition
or a second
Start Condition
. See Figure 31.
13.7
A read operation is initiated by the master with a
Start Condition
followed by the sensor’s
Device Address
and
Write
bit. When
the master receives an
Acknowledge
from the sensor it can
transmit the internal
Register Address
byte. The sensor will
respond with a second
Acknowledge
. The master must then
issue a new
Start Condition
followed by the sensor’s
Device
Address
and
read
bit. The sensor will respond with an Acknowl-
edged followed by the
Read Data
byte.
The read operation is completed when the master asserts a
Not
Acknowledge
followed by
Stop Condition
or a second
Start Con-
dition
. See Figure 32.
Read Operation
sda
sclk
S
P
start condition
stop condition
1
2
7
8
9
sda
sda
from sensor
sclk
MSB
ACK
ACK
START
S
Clock pulse
for ACK
sda
sclk
data line
stable;
data valid
change
of data
allowed
data line
stable;
data valid
Figure 30. Serial Bus Byte Format
Figure 31. Serial Bus Write Operation
Figure 32. Serial Bus Read Operation
sclk
sda
1
2
7
8
9
ACK
1
8
2
MSB
START
S
P
ack signal
from receiver
byte complete
clock line
held low
ACK
ack signal
from receiver
Address
W
S
A
Register
Address
A
Data
Byte
A
P
Device
bold
sensor action
Device
Address
S
A
Register
Address
Data
Byte
Device
Address
A
S
A
R
P
_
A
W
bold
sensor action
L
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