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參數(shù)資料
| 型號： | LM5067SD-2 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10 |
| 封裝： | LLP-10 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 690K |
| 代理商： | LM5067SD-2 |
30030930
FIGURE 3. Power Up Sequence (Current Limit only)
Operating Voltage
The LM5067 operating voltage is the voltage from VCC to
VEE. The maximum operating voltage is set by an internal
13V zener diode. With the IC connected as shown in Figure
1, the LM5067 controller operates in the voltage range be-
tween VEE and VEE+13V. The remainder of the system
voltage is dropped across the input resistor R
IN, which must
be selected to pass at least 2 mA into the LM5067 at the min-
imum system voltage.
Gate Control
The external N-channel MOSFET is turned on when the
GATE pin sources 52 A to enhance the gate. During normal
operation (t3 in Figure 3) Q1’s gate is held charged to ap-
proximately 13V above VEE, typically within 20 mV of the
voltage at VCC. If the maximum V
GS rating of Q1 is less than
13V, a lower voltage external zener diode must be added be-
tween the GATE and SENSE pins. The external zener diode
must have a forward current rating of at least 110 mA.
When the system voltage is initially applied (before the oper-
ating voltage reaches the POR
IT threshold), the GATE pin is
held low by a 110 mA pull-down current. The pull-down cur-
rent helps prevent an inadvertent turn-on of the MOSFET
through its drain-gate capacitance as the applied system volt-
age increases.
During the insertion time (t1 in Figure 3) the GATE pin is held
low by a 2.2 mA pull-down current. This maintains Q1 in the
off-state until the end of t1, regardless of the voltage at VCC
and UVLO.
Following the insertion time, during t2 in Figure 3, the gate
voltage of Q1 is modulated to keep the current or Q1’s power
dissipation level from exceeding the programmed levels. Cur-
rent limiting and power limiting are considered fault condi-
tions, during which the voltage on the TIMER pin capacitor
increases. If the current and power limiting cease before the
TIMER pin reaches 4V the TIMER pin capacitor is discharged,
and the circuit enters normal operation. See the Fault Timer
& Restart paragraph for details on the fault timer.
If the system input voltage falls below the UVLO threshold, or
rises above the OVLO threshold, the GATE pin is pulled low
by the 2.2 mA pull-down current to switch off Q1.
11
www.national.com
LM5067
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