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參數(shù)資料
| 型號： | LM5067SD-2 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10 |
| 封裝： | LLP-10 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 690K |
| 代理商： | LM5067SD-2 |
POWER GOOD PIN
During initial power up, the Power Good pin (PGD) is high until
the operating voltage (VCC – VEE) increases above
2V.
PGD then switches low, remaining low as the system voltage
and the operating voltage increase. After Q1 is switched on,
when the voltage at the OUT pin is within 1.23V of the SENSE
pin (Q1’s V
DS <1.23V), PGD switches high indicating the out-
put voltage is at, or nearly at, its final value. Any of the
following situations will cause PGD to switch low within
10
s:
- The V
DS of Q1 increases above 2.5V.
- The system input voltage decreases below the UVLO level.
- The system input voltage increase above the OVLO level.
- The TIMER pin increases to 4V due to a fault condition.
A pull-up resistor is required at PGD as shown in Figure 15.
The pull-up voltage (V
PGD) can be as high as 80V above VEE,
with transient capability to 100V, and can be higher or lower
than the system ground.
30030958
FIGURE 15. Power Good Output
If a delay is required at PGD, suggested circuits are shown in
Figure 16. In Figure 16a, capacitor C
PG adds delay to the ris-
ing edge, but not to the falling edge. In Figure 16b, the rising
edge is delayed by R
PG1 + RPG2 and CPG, while the falling
edge is delayed a lesser amount by R
PG2 and CPG. Adding a
diode across R
PG2 (Figure 16c) allows for equal delays at the
two edges, or a short delay at the rising edge and a long delay
at the falling edge.
30030959
FIGURE 16. Adding Delay to the Power Good Output Pin
Design-in Procedure
The recommended design-in procedure for the LM5067 is as
follows:
Determine the minimum and maximum system voltages
(VEE). Select the input resistor (R
IN) to provide at least 2
mA into the VCC pin at the minimum system voltage.The
resistor’s power rating must be suitable for its power
dissipation at maximum system voltage ((V
SYS – 13V)
2
/
R
IN).
Determine the current limit threshold (I
LIM). This threshold
must be higher than the normal maximum load current,
allowing for tolerances in the current sense resistor value
and the LM5067 Current Limit threshold voltage. Use
equation 1 to determine the value for R
S.
Determine the maximum allowable power dissipation for
the series pass FET (Q1), using the device’s SOA
information. Use equation 2 to determine the value for
R
PWR.
Determine the value for the timing capacitor at the TIMER
pin (C
T) using equation 3. The fault timeout period
(t
FAULT) must be longer than the circuit’s turn-on-
time
. The turn-on time can be estimated using the
equations in the Turn-on Time section of this data sheet,
but should be verified experimentally. Allow for tolerances
in the values of the external capacitors, sense resistor, and
the LM5067 Electrical Characteristics for the TIMER pin,
current limit and power limt. Review the resulting insertion
time, and the restart timing if the LM5067-2 is used.
Choose option A, B, C, or D from the UVLO, OVLO section
of the Application Information for setting the UVLO and
OVLO thresholds and hysteresis. Use the procedure in the
appropriate option to determine the resistor values at the
UVLO and OVLO pins.
Choose the appropriate voltage, and pull-up resistor, for
the Power Good output.
19
www.national.com
LM5067
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