參數(shù)資料
型號(hào)： LM5067SD-2
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10
封裝： LLP-10
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 690K
代理商： LM5067SD-2
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Current Limit
V
CL
Threshold voltage
SENSE - VEE voltage
44
50
56
mV
t
CL
Response time
SENSE - VEE stepped from 0 mV
to 80 mV
25
s
Circuit Breaker
V
CB
Threshold voltage
SENSE - VEE voltage
70
100
130
mV
t
CB
Response time
SENSE - VEE stepped from 0 mV
to 150 mV, time to GATE low, no
load
0.65
1.0
s
Power Limit (PWR Pin)
PWR
LIM
Power limit sense voltage (SENSE - VEE)
OUT - SENSE = 24V, R
PWR = 75
k
16.5
22
27.5
mV
I
PWR
PWR pin current
V
PWR = 2.5V
-23
A
Timer (TIMER Pin)
V
TMRH
Upper threshold
3.76
4
4.16
V
TMRL
Lower threshold
Restart cycles (LM5067-2)
1.18
1.25
1.32
V
End of 8th cycle (LM5067-2)
0.3
V
Re-enable threshold (LM5067-1)
0.3
V
I
TIMER
Insertion time current
TIMER pin = 2V
-9.5
-6
-2.5
A
Sink current, end of insertion time
TIMER pin = 2V
1.2
1.55
1.9
mA
Fault detection current
TIMER pin = 2V
-140
-85
-44
A
Sink current, end of fault time
0.9
2.5
4.25
A
DC
FAULT
Fault Restart Duty Cycle
LM5067-2
0.5
%
t
FAULT
Fault to GATE low delay
TIMER pin reaches 4.0V
15
s
Power Good (PGD Pin)
PGD
TH
Threshold measured at OUT - SENSE
Decreasing
1.162
1.23 1.285
V
Increasing, relative to decreasing
threshold
1.143
1.25 1.325
PGD
VOL
Output low voltage
I
SINK = 2 mA
60
150
mV
PGD
IOH
Off leakage current
V
PGD = 80V
5
A
Thermal Resistance (Note 6)
θ
JA
Junction to Ambient
MSOP package
94
°C/W
LLP package
52
θ
JC
Junction to Case
MSOP package
44
°C/W
LLP package
9.4
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics.
Note 2:
The human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
Note 3:
Current out of a pin is indicated as a negative value.
Note 4:
For detailed information on soldering plastic MSOP and LLP packages refer to the Packaging Databook available from National Semiconductor
Corporation.
Note 5:
Maximum continuous current into VCC is limited by power dissipation and die temperature. See the Thermal Considerations section.
Note 6:
Tested on a 4 layer JEDEC board with 2 vias under the package. See JEDEC standards JESD51-7 and JESD51-3. See the Thermal Considerations
section.
www.national.com
4
LM5067
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