參數(shù)資料
型號(hào)： LM3655TLX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, BGA25
封裝： 2.5 X 2.5 MM, MICRO SMD, 25 PIN
文件頁(yè)數(shù)： 5/21頁(yè)
文件大?。?/td> 833K
代理商： LM3655TLX
12.0 Discharge Control Functions (Continued)
12.3 UNDER-VOLTAGE CUT-OFF
Two thresholds for cell under-voltage detection are used to prevent the cell from being discharged below levels that could cause
irreversible damage. The higher level, Primary Under-Voltage, is designated V
PUV, and the secondary level is VSUV. Nominal
values are 2.350V and 1.98V respectively. When the V
PUV threshold is crossed, a timer is initiated. If the cell voltage remains
below V
PUV but above VSUV for the delay time
τ
PUV (nominally 64 ms), the IC enters sleep mode. The IC will go into sleep mode
with no time delay if the cell voltage drops below V
SUV.
In sleep mode, all of the sequential logic is reset to a standby state. The safety shunt circuits are still powered up in order to
protect the chip and cell from an accidental path for high energy to the V
IN pin. M4 control circuits are powered down (M4 remains
off).
Operating Current Parametric Specs
Unless otherwise noted, the following specifications apply over the Normal Temperature Range.
Specification
Test Conditions
Min
Typ
Max
Units
Quiescent Current w/no external power supply
“I
Q_DISG” @ 25C
V
CELL =VPUV to VTERMX
No Load at Radio B+, I
VIN =0,
V
DETECT = 0V, ICNTRL =0A
-20
30
A
Quiescent Current w/no external power supply
“I
Q_DISG” @ 20C < T < 60C
V
CELL =VPUV to VTERMX
No Load at Radio B+, I
CIN =0,
V
DETECT = 0V, ICNTRL =0A
-
50
A
Sleep Mode Current “I
Q_SLEEP” @ T = 25C
Sleep mode AND V
CELL =VPUV to 0V
No Load at Radio B+
V
DETECT = 0V, ICNTRL =0A
-
9.0
15
A
Sleep Mode Current “I
Q_SLEEP” @ Normal
Temperature Range
Sleep mode AND V
CELL =VPUV to 0V
No Load at Radio B+
V
DETECT = 0V, ICNTRL =0A
-
20
A
Primary Under Voltage “V
PUV” at CELL Pin
Time delay entry into sleep mode =
τ
PUV
2.275
2.350
2.425
V
Hibernation Delay “
τ
HIBERNATION”
223264
ms
Primary Under Voltage Delay “
τ
PUV”
446484
ms
Secondary Under Voltage “V
SUV” at CELL Pin
No delay entry into sleep mode
1.90
1.98
2.06
V
“V
CHRG-LOW VPUV =
CHRGLOW-PUV”
100
200
300
mV
12.4 POWER CUT OPERATION
A power cut is defined as momentary loss of contact between the battery/cell and the phone circuitry, typically caused by contact
bounce. During a power cut, the connection between the cell’s positive terminal and the IC’s CELL pin may be lost as well as the
ground connection between the cell’s negative terminal and the IC’s ground pins. During Power Cut the IC will go into the sleep
mode. Once the connection is re-established and the cell voltage is greater than V
CHRG_LOW (nominally 2.575V), the IC will power
up its internal circuitry and allow the operations (charging and discharging) to continue. A power cut is differentiated from an
under-voltage condition by monitoring the cell voltage level.
12.5 HIBERNATION MODE
When the cell is in its normal voltage range (> 2.575V), M4 is closed. Thus any radio current consumption can discharge the
battery. This is generally desired except when the phone is stored for a long time without use and without being charged. When
hibernation mode is enabled, then M4 is opened so that the battery cell will discharge only due to the consumption of this IC and
not because of any Radio B+ current consumption. When Hibernation is enabled, the IC will be put into ‘sleep’ which allows the
IC to have a smaller quiescent current when compared to ‘normal’ mode.
Hibernation mode is entered when HIB_EN is held high for a debounce period of 32 ms.
Hibernation mode is exited and M4 subsequently closed when a charger is connected to LM3655 or when the HIB_DISB input
pin goes low.
13.0 Safety Functions
13.1 INPUT OVER-VOLTAGE PROTECTION
13.1.1 Normal Operation (Q1 Control)
Under normal conditions, the Q1 pass device prevents excessively high voltages from reaching RADIO_B+. In the case of
full-rate charging, the external supply voltage will normally collapse to a level just above the cell voltage as the supply current limit
is reached. As charge current is reduced, the supply voltage may increase, but the voltage difference is dropped across Q1 as
LM3655
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13
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