
10.0 Pin Functions (Continued)
10.4 V
DETECT
This pin is coupled to the external power supply through a series resistance (R4). It is used to determine when an external source
(charger) is connected, which in turn initiates the device’s charge control logic. The CHRG_DETB output is set based on input to
this pin.
10.5 DISABLE
The phone can stop the charge current through use of the DISABLE logic input pin of the IC. Asserting a logic high on the
DISABLE Pin of the IC will force the control pin (CNTRL) to turn off the external Drive (Q2) and Pass (Q1) transistors so there
is no charge current to the cell. The DISABLE input can be driven high by the phone’s logic at any time to interrupt the charge
current. Use of the DISABLE pin during charging can allow the phone to measure the cell’s true voltage by peripheral circuitry
(without the presence of charge current input) if desired.
Additionally, a high-to-low transition on the DISABLE pin (thus re-enabling the charger operation), will reset the charge control
state machine.
10.6 CHEMISTRY
The CHEMISTRY pin provides a logic input to the IC that determines the termination threshold for Li-ion cell charging. A logic low
applied to this pin selects the lower charging threshold or termination voltage (V
TERML), a logic high selects the higher charging
threshold (V
TERMH).
Because different cell types may require slightly different charge termination thresholds, the LM3655 supports a pin-
programmable selection between two different settings. The lower threshold is nominally 4.10V, and the higher threshold is
nominally 4.16V.
10.7 HIB_EN
This pin provides a logic input to the IC that when held high during a debounce period of 32 mS, M4 will be latched open even
if the cell voltage is above V
CHARGE_LOW. This pin has a 10K pull-down resistor internal to the IC so that the IC will default on.
10.8 HIS_DIS
This pin provides a logic input to the IC that when held low momentarily, the latch holding M4 open is cleared allowing it to be
closed when the cell voltage is above V
CHARGE_LOW. This pin has a 100K pullup resistor to the CELL pin internal to the IC.
10.9 BATT_DETB
BATT_DETB indicates to the LM3655 IC that a cell is present in the system. This pin provides a logic input to the IC that when
held low, the IC will be able to detect the presence of a charger. There is a 100K pull-up resistor internal to the IC on this pin, which
is supplied from the charger (not from the cell).
A series 10K resistor is to be used between this pin and the removable battery to protect the IC against ESD.
10.10 CHRG_STATE
CHRG_STATE is an open-drain logic output to the phone, and can be used to provide a simple battery-metering indication during
charge mode. During charge mode, with current flowing into the cell, the Li-ion cell voltage cannot be used for an accurate
indication of state of charge. If a battery is at a relatively low state of charge, it will remain in the “full-rate” charge mode for some
period of time when connected to the external power supply. When the cell reaches a higher state of charge, the charge control
switches to the trickle/top-off mode. Thus, this signal is logic low during full-rate charge mode and high during the trickle/top-off
mode. The exact percentage of “full” at this crossover point will vary depending on many conditions, primarily full-rate charge
current level, but is expected to be >60% for typical use with a mid-rate charger.
This information can be used to provide a simple “charging” or “ready” indication by the system for the battery status meter during
charge. If combined with a timer, or other means of interaction by the system (such as periodic control of the DISABLE pin
combined with cell voltage measurements during periods of no current flow) a more complete metering method may be
implemented if desired.
10.11 CHRG_DET
This is an open-drain output to the phone’s power management IC that indicates the connection of an external power supply.
Typical application uses a 30K pull-up resistor to RADIO_B+. When a charger is detected, this output is pulled LOW by the
internal logic of the LM3655. This signal may be pulled up to a low-voltage logic rail such as 2.75V or 1.8V regulated voltage. It
is assumed that the voltage used to pull-up is no higher than the cell voltage.
10.12 CNTRL
This is an analog output to control Q2, the NPN drive transistor. The CNTRL output is adjusted to deliver the appropriate level of
current required by the charge algorithm for full-rate or trickle/top-off charging. During full-rate charging, CNTRL is set such that
Q1 will be saturated. During trickle/top-off mode, CNTRL will be set in order to maintain the appropriate cell clamp voltage (4.10V
or 4.16V as desired). Furthermore, if the power-monitoring circuit determines that excess power is being dissipated in, the CNTRL
signal will be further reduced to limit current flowing through Q1. This ensures that the Q1 pass device remains within safe power
dissipation limits.
LM3655
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