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參數(shù)資料
| 型號(hào)： | LM3101 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Secondary-Side PWM Controller |
| 中文描述： | 二次側(cè)PWM控制器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 319K |
| 代理商： | LM3101 |
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2:
The reference voltage is measured at the error amplifier’s output with the error amplifier connected as a non-inverting amplifier with a gain of one.
Note 3:
The temperature coefficients of V
REF
or F
O
are defined as the worst-case
D
V
REF
or
D
F
O
measured at Specified Temperatures divided by the total span of
the Specified Temperture Range (see graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum of maximum deviation.
Note 4:
The frequency of the internal oscillator is set by connecting a resistor, R
T
, from pin 1 to ground. See detailed description of this feature in the Pin-by-Pin
Description section or the Functional Description of this datasheet.
Note 5:
A resistor, R
SC
, is connected from pin 5 to the regulator’s output. See detailed description of this feature in the Pin-by-Pin Description section or the
Functional Description section of this datasheet.
Note 6:
For this test, the frequency of synchronization, F
SYNC
, is 600 kHz, C
SYNC
is 220 pF, and R
SYNC
is 1 k
X
. The internal oscillator will synchronize to an AC
signal that is 1.1 to 1.5 times the free running oscillator frequency, F
O
. See Functional Description section or Pin-by-Pin Description section for more detail on
synchronization.
Note 7:
I
COMP
is sourced from pin 6 (CMI). See Functional Description section or Pin-by-Pin Description section for more detail on current mode operation.
Note 8:
Minimum duty cycle is the smallest duty cycle that can be produced by the LM3101 in a given oscillator period. The controller can operate with effectively
zero duty cycleDit skips cycles if the regulation cannot be maintained with the minimum duty cycle. This means that the output voltage of the switching converter is
regulated down to no load.
Note 9:
The current sense time delay is the time span between an input applied to the CMI pin (pin 6) and the change of state of V
OUT
(pin 8) due to the input.
Note 10:
Both these specifications, %V
THC
and %V
THP
, are relative to the nominal feedback voltage, V
FB
, by the factor:
[
(V
TH
–V
FB
)/V
FB
]
.
Note 11:
An internal delay circuit prevents triggering of the overvoltage crowbar circuit, for pulse widths less than 400 ns, to ensure noise immunity.
Note 12:
This is the minimum supply voltage for which the power-on reset flag will continue to be valid (low).
Note 13:
For V
S
k
V
UV
, the output is offDit is in a high-impedance state.
Note 14:
A resistor/capacitor circuit is normally connected from the soft start circuit, pin 3, to ground. The circuit provides a slow or ‘‘soft’’ start of the IC by slowly
ramping the reference voltage from a lower initial value set by the resistor to its normal operating value. See detailed description of this feature in the Pin-by-Pin
Description section or the Functional Description section of this datasheet.
Connection Diagram and Ordering Information
14-Lead Package
Top View
TL/H/11436–2
For Surface Mount Package
Order Number LM3101M
See NS Package Number M14B
For DIP Package
Order Number LM3101N
See NS Package Number N14A
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM3101M | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Secondary-Side PWM Controller |
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