參數(shù)資料
型號: LM3101
廠商: National Semiconductor Corporation
英文描述: Secondary-Side PWM Controller
中文描述: 二次側(cè)PWM控制器
文件頁數(shù): 10/20頁
文件大?。?/td> 319K
代理商: LM3101
Functional Description
(Continued)
To operate under current mode or charge mode control,
insert a resistor, R
MC
, between the MC pin and ground, and
connect the CMI pin to the Current Mode Sense Circuit (see
Figure 4). At the MC pin, a voltage, proportional to the oscil-
lator ramp voltage, develops (see Figure 3). The voltage
ramp applied to R
MC
generates a current ramp, which is
duplicated on the CMI pin due to the current mirror. The
current ramp, which flows, out of the CMI pin to the resistor,
R
F
, is the compensation ramp, needed to stabilize convert-
ers operating at duty cycles above 50%. The slope of the
compensating ramp can be scaled by R
F
, which is connect-
ed between the CMI pin and the terminating resistor, R
S
, of
the current sense transformer. In all practical cases, R
F
will
be much greater than R
S
. For both control modes, the cur-
rent ramp provides slope compensation according to the
equation:
D
I
COMP
/
D
t
e
24
#
10
3
/(R
T
#
R
MC)
So, with R
T
equal 25 k
X
and R
MC
equal 6 k
X
, the compen-
sation ramp slope is:
D
I
COMP
/
D
t
e
24
#
10
3
/(25 k
X
#
6 k
X
)
e
160
m
A/
m
s.
[
m
A/
m
s,
X
]
.
The resistor R
F
together with the capacitor C
F
serves as an
RC filter for the leading edge spike of the current sense
waveform (the spike is caused by the output rectifier reverse
recovery and/or the winding capacitance of the power
transformer).
CHARGE MODE CONTROL
Under charge mode control, the current sense transformer
drives a capacitor, C
1
, that integrates the sensed switch
current on a cycle-by-cycle basis. Figure 5 shows the inte-
grating current sense circuitry and the simplified details of
the associated internal circuitry of the LM3101. Transistor
Q
1
discharges the integrating capacitor C
1
once every
switch cycleDduring the switch off-time (Q1 can provide up
to 20 mA of discharge current). Charge mode control yields
the fastest average current control loop.
TL/H/11436–10
TL/H/11436–11
FIGURE 5. Charge Mode Operation
10
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