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參數(shù)資料
| 型號： | LM1893N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | RES 250K-OHM 1% 0.125W THICK-FILM SMD-0805 5K/REEL-7IN-PA |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 576K |
| 代理商： | LM1893N |
Thermal Considerations
(Continued)
nal
i
JA
for an N package is 60
§
C/W, lower with good PC
board layout. Since P
D
is a relatively strong function of T
J
,
an iterative solution process starting with an initial guess for
T
J
is used. With the estimated T
J
, find the total supply cur-
rent found in the typical performance characteristics.
TL/H/6750–27
FIGURE 25. T
J
may be found by using the temperature
coefficient of pin 18 V
BE
if V
BE
is known at 25
§
C
Transmit-To-Receive
Switch-Over Time
An important figure-of-merit for a half-duplex CCT link, af-
fecting effective data rate, is the TX-to-RX switch time T
TR
.
Using the recommended component values gives this part a
nominal 2 bit-time (1 bit time
e
1/
[
2f
DATA
]
) over a wide
range of operating conditions, where the receiver requires 1
data transition. T
TR
cannot be decreased significantly but
does increase as noise filtering, especially via C
M
, is in-
creased. Impulse noise at switch, signals near the limiting
sensitivity, poor F
O
match between receiver and transmitter
because of poor trim or worst-case conditions, and the sta-
tistical nature of PLL signal acquisition may all contribute to
increase T
TR
to possibly 4 bit-times.
T
TR
is lower when a pair of LM1893’s handshake rapidly.
The receiver was designed to ‘‘remember’’ the RX-mode
DC operating points on C
M
and C
F
while in the TX mode.
Under noisy worst case conditions, C
M
will discharge to the
point of false operation after 35 bit-times in the TX mode
(1400 bit times with no noise and a nominal part, f
DATA
e
180 Hz). T
TR
is about 0.8 ms (proportional to the selected
F
O
) plus
(/2
bit-time.
The major components of T
TR
are described below for a
nominal 125 kHz F
O
, 180 Hz f
DATA
, lightly-loaded tank with
a Q of 20, and the circuit of Figure 4. The remote CCT has
been operating in the TX mode with a 26.6 V
PP
tank swing
and is now selected as a receiver. An incoming signal re-
quiring the ultimate receiver sensitivity immediately is placed
on the line.
First, the tank stored energy at the transmit frequency must
decay to a level below the 2.8 mV
PP
swing caused by the
0.14 mV
RMS
incoming line signal containing the information
to be received.
decay time
e
Q
q
F
O
ln
V
1
V
O
e
20
q
c
125 000
ln
26.6
0.0028
e
0.466 ms
(2)
That is 0.47 ms of delay (proportional to I/F
O
and Q).
Second, the PLL must acquire the signal; it must lock and
settle. Acquisition time is statistical and may take any length
of time, but average acquisition time depends on the loop
filter components C
F
and R
F
and the difference in center
frequencies,
D
F
O
, of the TX/RX pair. Using the recom-
mended C
F
and R
F
(47 nF and 6.2 k
X
) with a
g
4.4%
D
F
O
(a
g
100 mV DC offset on C
F
and R
F
), lock was measured
to take less than 50 cycles of F
O
. That is a 0.40 ms delay
(proportional to 1/F
O
).
Acquisition is incomplete until the second order PLL loop
settles. For the above-mentioned C
F
and R
F
, the loop natu-
ral frequency F
N
and damping factor are found to be
2.3 kHz and 1.0 respectively. Settling to within
g
25 mV of
the
g
100 mV DC offset change requires 2.7 periods of F
N
,
or 1.2 ms (a function of C
F
and R
F
).
Third, the RC lowpass filter introduces a 0.12 ms delay.
Fourth, C
M
must charge up to
g
(
±/6
)100
e
83 mV depend-
ing on the polarity of F
O
. Borderline data squaring with zero
noise immunity is possible with only
g
(
±/6
) 50 mV of charg-
ing. C
M
charge current is an asymptotic function approxi-
mated by assuming a 50
m
A charge current and the full 83
mV charge voltage. C
M
charge time is then 1.7 ms (propor-
tional to 1/f
DATA
).
Fifth, the impulse noise filter adds a
(/2
bit-time delay. Total
T
TR
is 3.9 ms plus
(/2
bit-time for a total of 1.9 bit-times at
360 Baud.
Receive-To-Transmit
Switch-Over Time
Assume the chip has been in the RX mode and the TX
mode is now selected. In less than 10
m
s, full output current
is exponentially building tank swing. 50% of full swing is
achieved in less than 10 cycles - or under 80
m
s at 125 kHz.
In the same 10
m
s that the output amp went on, the phase
detector and loop filter are disconnected and the modulator
input is enabled. FSK modulation is produced in 10
m
s after
switching to TX mode.
Power Line Impedance
Irrespective of how wide the limits on power line impedance
Z
L
are placed, there are no guarantees. However, since the
CCT design requires an estimate of the lowest expected line
impedance Z
LN
encountered for the most efficient transmit-
ter-to-line coupling, line impedance should be measured
and Z
L
limits fixed to a given confidence level. Reasonable
values for T
1
turns ratio, loaded Q, and tank resonant fre-
quency pull F
Q
may be found to enable a CCT system de-
sign that functions with the overwhelming majority of power
lines.
A limited sampling of Z
L
was made, during the LM1893 de-
sign, of residential and commercial 115V 60 Hz power line.
Data was also drawn from the research of Nicholson and
Malack (reference 1), among others, to produce Figures 26
and 27. All measured impedances are contained within the
shaded portions of Figure 27. A nominal 3.5, 7.0 and 14
X
Z
LN
is used throughout the application information with a
nominal 45
§
phase angle (0
§
is sometimes used for simplici-
ty).
TL/H/6750–28
FIGURE 26. Measured line impedance range for
residential and commercial 115V, 60 Hz lines
15
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