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參數(shù)資料
| 型號： | LM1893N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | RES 250K-OHM 1% 0.125W THICK-FILM SMD-0805 5K/REEL-7IN-PA |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 576K |
| 代理商： | LM1893N |
Breadboarding Tips
(Continued)
D When evaluating CCT system noise performance on a
real power line, it is desirable to vary the signal ampli-
tude to the receiver. This is not easy. An in-line line-
proof L-pad is fine except that the line impedance is un-
known and variable and so the L-pad will rarely match.
Instead, the power output of a chip transmitter may be
controlled using the circuit ofFigure 23. This circuit con-
trols the ALC.
D It is sometimes desirable to place impulse noise on the
line. A simple light dimmer with a 100 W light bulb load
produces representative impulse noise.
D Do not allow peak currents of over 1 A through the 5.6 V
Zener. In other words, don’t short charged capacitors
into this low-impedance device. Take care not to mo-
mentarily short pins 10 and 11 - chip damage may result.
D Figure 24 shows some typical signals beginning with se-
rial data transmitted to received signal.
Tuning Procedure
This procedure applies to circuits similar toFigure 4 LM1893
or LM2893 circuit.
First, trim F
O
by putting the chip in the TX mode, setting a
logical high data input, and measuring the TX high frequen-
cy, 1.022 F
O
, on the Carrier I/O using these steps:
1. Take pin 17 to a logic low.
2. Take pin 5 to a logic high.
3. Place a counter on pin 10.
4. Adjust R
O
on pin 18 for F
e
1.022F
O
.
Second, the line transformer is tuned. The chip is placed in
the TX mode, a resistive line load is connected to disable
the ALC by reducing tank voltage swing below its limit. FSK
data is then passed through the tank so that the tank enve-
lope may be adjusted for equal amplitude for high and low
data frequency.
1. Take pin 5 to a logic high.
2. Place a logic-level square wave at or below the receiver’s
maximum data rate on pin 17.
3. Temporarily place a 330
X
resistor across the tank.
4. Place a scope on pin 10.
5. Adjust the transformer slug for the least envelope modu-
lation.
In lieu of the 330
X
resistive load, T
1
may be coupled to the
power line to better simulate actual load and tank pull condi-
tions during tank tuning. Alternatively, a passive network
representing an average line impedance may be connected
to the line side of T
1
. The circuit ofFigure 23 should then be
used to defeat the leveling effect of the ALC.
TL/H/6750–26
FIGURE 23. A means of transmitter output amplitude
control is shown
Thermal Considerations
It is desirable to place the largest possible signal on the
power line for maximum range, limited only by the chip pow-
er dissipation and maximum junction temperature T
J
. The
falling output power at elevated T
J
allows a more optimal
power output - high power at low T
J
and lower power at high
T
J
for chip self-protection. However, it is still possible to
exceed the maximum T
J
within the specified ambient tem-
perature limit (T
A
e
85
§
C) under worst case conditions of
100% TX duty cyle, high supply, shorted load, poor PC
board layout (with small copper foil area), and an above
nominal current part. Under those conditions, a part may
dissipate 2140 mW, reaching a T
J
e
170
§
C worst-case (ad-
mittedly a rare occurrence). Proper system design includes
the measurement or calculation of T
J
max. to guarantee
function under worst-case operation. Like all devices with
failure modes modeled by the Arrhenius model, the high
chip reliability is further enhanced by keeping the die tem-
perature mercifully below the absolute maximum rating.
A direct method of measuring operating junction tempera-
ture is to measure the V
BE
voltage on pin 18, which is al-
ways available under all operating modes. The graph ofFig-
ure 25 may be used to find T
J
, knowing V
BE
at the operating
point in question and V
BE
at T
A
e
T
J
e
25
§
C. V
BE
is found
by powering up a chip (in RX mode) that has been dissipat-
ing zero power at some T
A
for some time and measuring
V
BE
in less than 1 s (for better than 5
§
C accuracy).
Alternately, T
J
may be calculated using:
T
J
e
T
A
a
i
JA
P
D
where
i
JA
is 75
§
C/W for the plastic (N) package using a
socket. That
i
JA
value is for a high confidence level; nomi-
(1)
TL/H/6750–23
FIGURE 24. Oscillogram revealing signals at several important nodes under weak signal (0.5 mV
RMS
) conditions with
SCR spikes on an otherwise quiet 115 V, 60 Hz power line. The signals are: 1) transmitted data, 2) RX carrier on the
tuned transformer, 3) demodulated signal from the PLL after passing thru circuit ofFigure 22, 4) signal after RC
lowpass, 5) data at impulse noise filter integrator, and 6) received data. Horizontal scale is 10 ms per div.
14
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