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參數(shù)資料
| 型號： | LM1229 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | I2C Compatible CMOS TV RGB and Deflection Processor |
| 中文描述： | I2C兼容的CMOS電視RGB和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 20/27頁 |
| 文件大?。?/td> | 969K |
| 代理商： | LM1229 |
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Microcontroller Interface
(Continued)
conductor may use some additional addresses for produc-
tion testing. Writing to an address outside the ranges shown
here could have unpredictable or even destructive results.
Note the address gap between the RGB and deflection
control registers. This allows for future expansion of each
without changing existing registers.
Register bits indicated by an “X” are not used and should be
written to with 0’s when the register is updated.
TABLE 5. RGB Application Registers
Register
RED GAIN
GREEN GAIN
BLUE GAIN
CONTRAST
DAC 1
DAC 2
DAC 3
BRIGHTNESS
OFFSET
GLOBAL
OSD TRANS
OSD
RESET
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
Default
0x60
0x60
0x60
0x60
0x00
0x00
0x00
0x80
0x0C
0x00
0x00
0x02
0x00
Bit 7
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
RGAIN[6:0]
GGAIN[6:0]
BGAIN[6:0]
CONTRAST[6:0]
DAC1[7:0]
DAC2[7:0]
DAC3[7:0]
BRIGHTNESS[7:0]
X
VB
CLAMP
TRANS[6:0]
DA
TRANS
X
Bit 2
Bit 1
Bit 0
X
X
X
X
DC_Offset[3:0]
HB
INCR
X
OOR
X
DCF
PSAVE
BLANK
X
X
AUX
X
X
X
OSD_Cont[1:0]
X
X
SRST
TABLE 6. Deflection Application Registers
Register
STATUS
HPOS
HEHT
PAR
PIN_BAL
VSIZE
VEHT
C
S
VPOS
HSIZE
PIN
T_CORNER
B_CORNER
TRAP
DYN_FOCUS
SYNCPOL
VBLANK
Addr
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
Default
N/A
0x40
0xA8
0x80
0x80
0x80
0x88
0x40
0x00
0x80
0x40
0x40
0x40
0x40
0x40
0x40
0x3B
0x00
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
H_POS[7:0]
HPCOff
PAR[7:0]
PIN_BAL[7:0]
VSIZE[7:0]
Bit 3
VPROT
Bit 2
XRay
Bit 1
FBP
Bit 0
HLOCK
EQPRM
XRayOff
HOff
EHTEN
POL
HEHT[1:0]
VEHT2[7:4]
VEHT1[3:0]
X
X
C[6:0]
S[6:0]
VPOS[7:0]
X
X
X
X
X
X
X
X
HSIZE[6:0]
PIN[6:0]
T_CORNER[6:0]
B_CORNER[6:0]
TRAP[6:0]
DYN_FOCUS[6:0]
V1D
VBLANK[7:0]
X
VPD
V2D
SERV
VPOL
HPOL
Application Register Detail
RED Gain Control
Register
RED GAIN
Addr
0x00
Bit 7
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RGAIN[6:0]
Bits 6–0 Sets the gain level of the red video channel. A value of 0x7F generates the maximum red gain. A value of 0x00
generates the minimum red gain.
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