參數(shù)資料
型號: LH79520N0Q000B1
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH79520N0Q000B1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1017-1.html<1<Always Pb-free,;
文件頁數(shù): 24/59頁
文件大?。?/td> 666K
代理商: LH79520N0Q000B1
LH79520
System-on-Chip
24
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
AC Specifications
All signals described in Table 8 relate to transitions
after a reference clock signal. The illustration in Figure
7 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
The reference clock signals in this design are:
HCLK, the System Bus clock
PCLK, the Peripheral Bus clock (locked to HCLK in
the LH79520)
SSPCLK, the Synchronous Serial Interface clock
UARTCLK, the UART Interface clock
LCDDCLK, the LCD Data clock from the
LCD Controller
and SDCLK, the SDRAM clock.
All signal transitions are measured from the 50 %
point of the clock to the 50 % point of the signal. See
Figure 7.
For outputs from the LH79520, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 8.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 8.
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 8.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the memory output must be held valid
from the rising edge of the reference clock signal. Min-
imum requirements are shown in Table 8.
Figure 7. LH79520 Signal Timing
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
79520-34
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