參數(shù)資料
型號(hào): LH79520N0Q000B1
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH79520N0Q000B1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1017-1.html<1<Always Pb-free,;
文件頁(yè)數(shù): 16/59頁(yè)
文件大?。?/td> 666K
代理商: LH79520N0Q000B1
LH79520
System-on-Chip
16
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
SYSTEM DESCRIPTIONS
ARM720T Processor
The LH79520 microcontroller features the ARM720T
cached core with an Advanced High-Performance Bus
(AHB) interface. The ARM720T features:
32-bit ARM7TDMI RISC Core
8 kB Cache
MMU (Windows CE enabled)
The processor is a member of the ARM7T family of
processors. For more information, see the ARM docu-
ment, ‘ARM720T (Rev 3) Technical Reference Manual’,
available on NXP’s’s website at www.nxp.com.
The LH79520 MMU provides a means to map Phys-
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is con-
strained by hardware to specific addresses, to be reor-
ganized at addresses identified by the user. These user
identified locations are called Virtual Addresses (VA).
When the MMU is enabled, Code and Data must be
built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU is
directly controlled through the System Control Copro-
cessor, Coprocessor 15 (CP15). The MMU is indirectly
controlled by a Translation Table (TT) and Page Tables
(PT) prepared by the user and established using a por-
tion of physical memory dedicated by the user to stor-
ing the TT and PT’s.
Figure 3. LH79520 Application Diagram Example
CODEC
TOUCH
SCREEN
CONTR.
DMA
FLASH/
SRAM/
SDRAM
IMAGER
SSP
STN/
TFT/AD-TFT
PIO
IR
PWM
UART
UART
LH79520
MEMORY
CARD
INTERFACE
FLASH
CARD
79520-6A
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