參數(shù)資料
型號： LFXP20E-5FN484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
中文描述： FPGA, 2464 CLBS, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù)： 88/130頁
文件大?。?/td> 1312K
代理商： LFXP20E-5FN484C
November 2007
Data Sheet DS1001
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
DS1001 Pinouts_02.5
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
I/O
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
Some of these user programmable pins are shared with special function pins.
These pin when not used as special purpose pins can be programmed as I/
Os for user logic.
During configuration, the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
GSRN
I
Global RESET signal. (Active low). Any I/O pin can be configured to be
GSRN.
NC
—
No connect.
GND
—
GND - Ground. Dedicated Pins.
VCC
—
VCC - The power supply pins for core logic. Dedicated Pins.
VCCAUX
—
VCCAUX - The Auxiliary power supply pin. It powers all the differential and ref-
erenced input buffers. Dedicated Pins.
VCCP0
—
Voltage supply pins for ULM0PLL (and LLM1PLL
1).
VCCP1
—
Voltage supply pins for URM0PLL (and LRM1PLL
1).
GNDP0
—
Ground pins for ULM0PLL (and LLM1PLL
1).
GNDP1
—
Ground pins for URM0PLL (and LRM1PLL
1).
VCCIOx
—VCCIO - The power supply pins for I/O bank x. Dedicated Pins.
VREF1(x), VREF2(x)
—
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as VREF inputs. When not used, they may be used as I/O pins.
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_PLL[T, C]_IN_A
—
Reference clock (PLL) input Pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A, B, C...at each side.
[LOC][num]_PLL[T, C]_FB_A
—
Optional feedback (PLL) input Pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A, B, C...at each side.
PCLK[T, C]_[n:0]_[3:0]
—
Primary Clock Pads, T = true and C = complement, n per side, indexed by
bank and 0,1, 2, 3 within bank.
[LOC]DQS[num]
—
DQS input Pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = Ball
function number. Any pad can be configured to be DQS output.
LatticeXP Family Data Sheet
Pinout Information
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