參數資料
型號: LFXP20E-5FN484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
中文描述: FPGA, 2464 CLBS, PBGA484
封裝: 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數: 34/130頁
文件大?。?/td> 1312K
代理商: LFXP20E-5FN484C
November 2007
Data Sheet DS1001
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
7-1
Revision History
Date
Version
Section
Change Summary
February 2005
01.0
Initial release.
April 2005
01.1
Architecture
EBR memory support section updated with clarification.
May 2005
01.2
Introduction
Added TransFR Reconfiguration to Features section.
Architecture
Added TransFR section.
June 2005
01.3
Pinout Information
Added pinout information for LFXP3, LFXP6, LFXP15 and LFXP20.
July 2005
02.0
Introduction
Updated XP6, XP15 and XP20 EBR SRAM Bits and Block numbers.
Architecture
Updated Per Quadrant Primary Clock Selection figure.
Added Typical I/O Behavior During Power-up section.
Updated Device Configuration section under Configuration and Testing.
DC and Switching
Characteristics
Clarified Hot Socketing Specification
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Added Programming and Erase Flash Supply Current table
Added LVDS Emulation section. Updated LVDS25E Output Termination
Example figure and LVDS25E DC Conditions table.
Updated Differential LVPECL diagram and LVPECL DC Conditions
table.
Deleted 5V Tolerant Input Buffer section. Updated RSDS figure and
RSDS DC Conditions table.
Updated sysCONFIG Port Timing Specifications
Updated JTAG Port Timing Specifications. Added Flash Download
Time table.
Pinout Information
Updated Signal Descriptions table.
Updated Logic Signal Connections Dual Function column.
Ordering Information
Added lead-free ordering part numbers.
July 2005
02.1
DC and Switching
Characteristics
Clarification of Flash Programming Junction Temperature
August 2005
02.2
Introduction
Added Sleep Mode feature.
Architecture
Added Sleep Mode section.
DC and Switching
Characteristics
Added Sleep Mode Supply Current Table
Added Sleep Mode Timing section
Pinout Information
Added SLEEPN and TOE signal names, descriptions and footnotes.
Added SLEEPN and TOE to pinout information and footnotes.
Added footnote 3 to Logic Signal Connections tables for clarification on
emulated LVDS output.
September 2005
03.0
Architecture
Added clarification of PCI clamp.
Added clarification to SLEEPN Pin Characteristics section.
DC and Switching
Characteristics
DC Characteristics, added footnote 4 for clarification. Updated Supply
Current (Sleep Mode), Supply Current (Standby), Initialization Supply
Current, and Programming and Erase Flash Supply Current typical
numbers.
LatticeXP Family Data Sheet
Revision History
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